NB3N1200K, NB3W1200L 3.3 V 100/133 MHz Differential 1:12 HCSL or Push-Pull Clock ZDB/Fanout Buffer for PCle www.onsemi.com Description The NB3N1200K and NB3W1200L differential clock buffers are DB1200Z and DB1200ZL compliant and are designed to work in conjunction with a PCIe compliant source clock synthesizer to provide pointtopoint clocks to multiple agents. The device is capable of distributing the reference clocks for Intel QuickPath Interconnect 64 1 (Intel QPI & UPI), PCIe Gen1/Gen2/Gen3/Gen4, SAS, SATA, and Intel Scalable Memory Interconnect (Intel SMI) applications. The QFN64 VCO of the device is optimized to support 100 MHz and 133 MHz MN SUFFIX CASE 485DH frequency operation. The NB3N1200K and NB3W1200L utilize pseudoexternal feedback topology to achieve low inputto output delay variation. The NB3N1200K is configured with the HCSL buffer MARKING DIAGRAMS type, while the NB3W1200L is configured with the lowpower NMOS PushPull buffer type. 1 1 Features NB3N NB3W 1200K 1200L 12 Differential Clock Output Pairs 0.7 V AWLYYWWG AWLYYWWG HCSL Compatible Outputs for NB3N1200K LowPower NMOS PushPull Compatible Outputs for NB3W1200L Optimized 100 MHz and 133 MHz Operating Frequencies to Meet NB3x1200x= Specific Device Code The Next Generation PCIe Gen2/Gen3/Gen4 and Intel QPI & UPI A = Assembly Location WL = Wafer Lot Phase Jitter YY = Year DB1200Z and DB1200ZL Compliant WW = Work Week 3.3 V 5% Supply Voltage Operation G = PbFree Package FixedFeedback for Lowest InputToOutput Delay Variation SMBus Programmable Configurations to Allow Multiple Buffers in a ORDERING INFORMATION Single Control Network PLL Bypass Configurable for PLL or Fanout Operation Device Package Shipping Programmable PLL Bandwidth NB3N1200KMNG QFN64 260 Units / (PbFree) Tray 2 Trilevel Addresses Selection (9 SMBUS Addresses) NB3N1200KMNTXG QFN64 1000 / Tape & Individual OE Control Pin for Each of 12 Outputs (PbFree) Reel 50 ps Max OutputtoOutput Skew Performance NB3W1200LMNG QFN64 260 Units / 50 ps Max CycletoCycle Jitter (PLL mode) (PbFree) Tray 100 ps Input to Output Delay Variation Performance NB3W1200LMNTXG QFN64 1000 / Tape & QFN 64pin Package, 9 mm x 9 mm (PbFree) Reel Spread Spectrum Compatible: Tracks Input Clock Spreading for Low For information on tape and reel specifications, EMI including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification 0C to +70C Ambient Operating Temperature Brochure, BRD8011/D. These Devices are PbFree and are RoHS Compliant Semiconductor Components Industries, LLC, 2017 1 Publication Order Number: July, 2017 Rev. 3 NB3N1200K/DNB3N1200K, NB3W1200L 12 OE 11:0 FB OUT* FB OUT * DIF 11:0 SSC Compatible MUX PLL DIF 11:0 CLK IN CLK IN 100M 133M HBW BYPASS LBW SA 0 Control SA 1 Logic PWRGD/PWRDN SDA SCL IREF** * FB OUT pins are for NB3N1200K only they are NC for NB3W1200L R ** IREF pin is for NB3N1200K only it is NC for NB3W1200L REF Figure 1. Simplified Block Diagram www.onsemi.com 2