Freescale Semiconductor Document Number: MC9RS08LE4 Rev. 3, 12/2009 Data Sheet: Technical Data MC9RS08LE4 28 W-SOIC Case 751F TBD MC9RS08LE4 Features: Breakpoint capability to allow single breakpoint setting during in-circuit debugging 8-Bit RS08 Central Processor Unit (CPU) Peripherals Up to 20 MHz CPU at 2.7 V to 5.5 V across temperature LCD Up to 8 14 or 4 18 segments compatible range of 40C to 85C with 5 V or 3 V LCD glass displays using on-chip Subset of HC08 instruction set with added BGND resistor bias network functional in wait, stop modes for instructions very low power LCD operation frontplane and On-Chip Memory backplane pins multiplexed with GPIO functions 4 KB flash memory read/program/erase over full selectable frontplane and backplane configurations operating voltage and temperature ADC 8-channel, 10-bit resolution 2.5 s conversion 256-byte random-access memory (RAM) time automatic compare function 1.7 mV/C Security circuitry to prevent unauthorized access to flash temperature sensor internal bandgap reference channel memory contents operation in stop fully functional from 2.7 V to 5.5 V. Power-Saving Modes TPM Two 2-channel 16-bit timer/pulse-width Wait and stop modulator (TPM) modules selectable input capture, Clock Source Options output compare, or buffered edge- or center-aligned Oscillator (XOSC) Loop-control Pierce oscillator PWM on each channel crystal or ceramic resonator range of 31.25 kHz to SCI One serial communications interface module 39.0625 kHz or 1 MHz to 20 MHz with optional 13-bit break LIN extensions Internal Clock Source (ICS) Internal clock source KBI 8-pin keyborad interrupt module module containing a frequency-locked-loop (FLL) Input/Output controlled by internal or external reference precision 26 GPIOs including 1 output-only pin and 1 input-only trimming of internal reference allows 0.2% resolution pin and 2% deviation over temperature and voltage Hysteresis and configurable pullup device on all input supports bus frequencies up to 10 MHz pins configurable slew rate and drive strength on all System Protection output pins Watchdog computer operating properly (COP) reset Package Options with option to run from dedicated 1 kHz internal clock 28-pin SOIC source or bus clock Low-voltage detection with reset or interrupt Selectable trip points Illegal opcode detection with reset Illegal address detection with reset Flash memory block protection Development Support Single-wire background debug interface This document contains information on a product under development. Freescale reserves the right to change or discontinue this product without notice. Freescale Semiconductor, Inc., 2008-2009. All rights reserved.Table of Contents 1 MCU Block Diagram .3 3.8 External Oscillator (XOSC) Characteristics . 16 2 Pin Assignments 3 3.9 Internal Clock Source (ICS) Characteristics 17 3 Electrical Characteristics .5 3.10 AC Characteristics 17 3.1 Introduction .5 3.10.1 Control Timing . 17 3.2 Parameter Classification .5 3.10.2 TPM Module Timing . 18 3.3 Absolute Maximum Ratings 6 3.11 ADC Characteristics 19 3.4 Thermal Characteristics .6 3.12 Flash Specifications . 21 3.5 ESD Protection and Latch-Up Immunity .7 4 Ordering Information . 23 3.6 DC Characteristics .8 5 Mechanical Drawings 24 3.7 Supply Current Characteristics .14 Revision History To provide the most up-to-date information, the revision of our documents on the World Wide Web will be the most current. Your printed copy may be an earlier revision. To verify you have the latest information available, refer to: