Document Number: P4080EC Freescale Semiconductor Rev. 3, 06/2012 Data Sheet: Technical Data P4080 QorIQ Integrated Processor FC-PBGA1295 37.5 mm x 37.5 mm Hardware Specifications The P4080 QorIQ integrated communication processor Enhanced secure digital host controller (SD/MMC) combines eight Power Architecture processor cores with Enhanced serial peripheral interfaces (eSPI) high-performance data path acceleration logic and network High-speed USB controller (USB 2.0) and peripheral bus interfaces required for networking, Host and device support telecom/datacom, wireless infrastructure, and mil/aerospace Enhanced host controller interface (EHCI) applications. ULPI interface to PHY Data Path Acceleration Architecture (DPAA) incorporating This chip can be used for combined control, data path, and acceleration for the following functions: application layer processing in routers, switches, base station Frame manager (FMan) for packet parsing, controllers, and general-purpose embedded computing. Its classification, and distribution high level of integration offers significant performance Queue manager (QMan) for scheduling, packet benefits compared to multiple discrete devices, while also sequencing, and congestion management greatly simplifying board design. Hardware buffer manager (BMan) for buffer allocation This chip includes the following function and features: and de-allocation Encryption/decryption (SEC 4.0) Eight e500-mc Power Architecture cores, each with a Regex pattern matching (PME 2.0) backside 128 KB L2 cache with ECC 1295 FC-PBGA package Three levels of instructions: user, supervisor, and hypervisor Independent boot and reset Secure boot capability CoreNet fabric supporting coherent and non-coherent transactions amongst CoreNet end-points A frontside 2 MB L3 Cache with ECC CoreNet bridges between the CoreNet fabric the I/Os, data path accelerators, and high and low speed peripheral interfaces Two 10-Gigabit Ethernet (XAUI) controllers Eight 1-Gigabit Ethernet controllers Two 64-bit DDR2/DDR3 SDRAM memory controllers with ECC Multicore programmable interrupt controller (MPIC) 2 Four I C controllers Four 2-pin UARTs or two 4-pin UARTs Two 4-channel DMA engines Enhanced local bus controller (eLBC) Three PCI Express 2.0 controllers/ports Two serial RapidIO 1.2 controllers/ports 2011-2012 Freescale Semiconductor, Inc. All rights reserved.Table of Contents 1 Pin Assignments and Reset States .3 2.19 GPIO . 100 1.1 1295 FC-PBGA Ball Layout Diagrams 3 2.20 High-Speed Serial Interfaces (HSSI) . 101 1.2 Pinout List 9 3 Hardware Design Considerations 129 2 Electrical Characteristics 52 3.1 System Clocking 129 2.1 Overall DC Electrical Characteristics 52 3.2 Supply Power Setting 136 2.2 Power Sequencing 57 3.3 Power Supply Design 138 2.3 Power Down Requirements 59 3.4 Decoupling Recommendations . 139 2.4 Power Characteristics 59 3.5 SerDes Block Power Supply Decoupling 2.5 Thermal .62 Recommendations . 139 2.6 Input Clocks .63 3.6 Connection Recommendations . 140 2.7 RESET Initialization .65 3.7 Recommended Thermal Model . 148 2.8 Power-on Ramp Rate 66 3.8 Thermal Management Information 148 2.9 DDR2 and DDR3 SDRAM Controller 66 4 Package Information 150 2.10 eSPI .74 4.1 Package Parameters for the P4080 FC-PBGA . 150 2.11 DUART .76 4.2 Mechanical Dimensions of the P4080 FC-PBGA . 151 2.12 Ethernet: Data Path Three-Speed Ethernet (dTSEC), 5 Security Fuse Processor . 152 Management Interface 1 and 2, IEEE Std 1588 77 6 Ordering Information 152 2.13 USB 84 6.1 Part Numbering Nomenclature . 152 2.14 Enhanced Local Bus Interface .87 6.2 Orderable Part Numbers Addressed by This 2.15 Enhanced Secure Digital Host Controller (eSDHC) .92 Document . 153 2.16 Programmable Interrupt Controller (PIC) Specifications94 7 Revision History . 155 2.17 JTAG Controller .95 2 2.18 I C .97 P4080 QorIQ Integrated Processor Hardware Specifications, Rev. 3 2 Freescale Semiconductor