HEF4053B Triple single-pole double-throw analog switch Rev. 11 11 September 2014 Product data sheet 1. General description The HEF4053B is a triple single-pole double-throw (SPDT) analog switch, suitable for use as an analog or digital multiplexer/demultiplexer. Each switch has a digital select input (Sn), two independent inputs/outputs (nY0 and nY1) and a common input/output (nZ). All three switches share an enable input (E). A HIGH on E causes all switches into the high-impedance OFF-state, independent of Sn. V and V are the supply voltage connections for the digital control inputs (Sn and E). DD SS The V to V range is 3 V to 15 V. The analog inputs/outputs (nY0, nY1 and nZ) can DD SS swing between V as a positive limit and V as a negative limit. V V may not DD EE DD EE exceed 15 V. Unused inputs must be connected to V , V , or another input. For DD SS operation as a digital multiplexer/demultiplexer, V is connected to V (typically EE SS ground). V and V are the supply voltage connections for the switches. EE SS 2. Features and benefits Fully static operation 5 V, 10 V, and 15 V parametric ratings Standardized symmetrical output characteristics Specified from 40 C to +125 C Complies with JEDEC standard JESD 13-B 3. Applications Analog multiplexing and demultiplexing Digital multiplexing and demultiplexing Signal gating 4. Ordering information Table 1. Ordering information All types operate from 40 C to +125 C. Type number Package Name Description Version HEF4053BP DIP16 plastic dual in-line package 16 leads (300 mil) SOT38-4 HEF4053BT SO16 plastic small outline package 16 leads body width 3.9 mm SOT109-1 HEF4053BTT TSSOP16 plastic thin shrink small outline package 16 leads body width 4.4 mm SOT403-1HEF4053B NXP Semiconductors Triple single-pole double-throw analog switch 5. Functional diagram E V DD 6 16 13 1Y1 LOGIC S1 11 12 1Y0 LEVEL DECODER CONVERSION 14 1Z 1 2Y1 LOGIC S2 10 2 2Y0 LEVEL CONVERSION 6 < 15 2Z 6 < 6 3 3Y1 < < LOGIC S3 9 5 3Y0 LEVEL CONVERSION < 43Z < ( 87 V V 001aae124 SS EE Fig 1. Logic symbol Fig 2. Functional diagram nZ nY1 LEVEL Sn CONVERTER nY0 LEVEL E CONVERTER to other multiplexers/demultiplexers 001aae645 Fig 3. Logic diagram (one multiplexer/demultiplexer) HEF4053B All information provided in this document is subject to legal disclaimers. NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 11 11 September 2014 2 of 20 DDH = = =