74LVC1G08GW-Q100

74LVC1G08-Q100 Single 2-input AND gate Rev. 3 25 January 2019 Product data sheet 1. General description The 74LVC1G08-Q100 provides one 2-input AND function. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V applications. Schmitt trigger action at all inputs makes the circuit tolerant of slower input rise and fall time. This device is fully specified for partial power-down applications using I . The I circuitry OFF OFF disables the output, preventing the damaging backflow current through the device when it is powered down. This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications. 2. Features and benefits Automotive product qualification in accordance with AEC-Q100 (Grade 1) Specified from -40 C to +85 C and from -40 C to +125 C Wide supply voltage range from 1.65 V to 5.5 V High noise immunity Complies with JEDEC standard: JESD8-7 (1.65 V to 1.95 V) JESD8-5 (2.3 V to 2.7 V) JESD8-B/JESD36 (2.7 V to 3.6 V) 24 mA output drive (V = 3.0 V) CC CMOS low power consumption Latch-up performance 250 mA Direct interface with TTL levels Inputs accept voltages up to 5 V ESD protection: MIL-STD-883, method 3015 exceeds 2000 V HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-A exceeds 200 V (C = 200 pf, R = 0 ) 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74LVC1G08GW-Q100 -40 C to +125 C TSSOP5 plastic thin shrink small outline package 5 leads SOT353-1 body width 1.25 mm 74LVC1G08GV-Q100 -40 C to +125 C SC-74A plastic surface-mounted package 5 leads SOT753 74LVC1G08GM-Q100 -40 C to +125 C XSON6 plastic extremely thin small outline package SOT886 no leads 6 terminals body 1 1.45 0.5 mmNexperia 74LVC1G08-Q100 Single 2-input AND gate 4. Marking Table 2. Marking Type number Marking code 1 74LVC1G08GW-Q100 VE 74LVC1G08GV-Q100 V08 74LVC1G08GM-Q100 VE 1 The pin 1 indicator is located on the lower left corner of the device, below the marking code. 5. Functional diagram A 1 1 B & Y 4 4 Y 2 A 2 B mna113 mna114 mna221 Fig. 1. Logic symbol Fig. 2. IEC logic symbol Fig. 3. Logic diagram 6. Pinning information 6.1. Pinning 74LVC1G08 74LVC1G08 B 1 6 V CC B 1 5 V CC A 2 5 n.c. A 2 GND 3 4 Y GND 3 4 Y 001aab639 001aab638 Transparent top view Fig. 4. Pin configuration SOT353-1 (TSSOP5) and SOT753 (SC-74A) Fig. 5. Pin configuration SOT886 (XSON6) 6.2. Pin description Table 3. Pin description Symbol Pin Description TSSOP5, SC-74A XSON6 B 1 1 data input A 2 2 data input GND 3 3 ground (0 V) Y 4 4 data output n.c. - 5 not connected V 5 6 supply voltage CC 74LVC1G08 Q100 All information provided in this document is subject to legal disclaimers. Nexperia B.V. 2019. All rights reserved Product data sheet Rev. 3 25 January 2019 2 / 12