74CBTLV3245BQ,115

74CBTLV3245-Q100 8-bit bus switch with output enable Rev. 4 7 May 2020 Product data sheet 1. General description The 74CBTLV3245-Q100 is an 8-pole, single-throw bus switch. The device features a single output enable input (OE) that controls eight switch channels. The switches are disabled when OE is HIGH. Schmitt-trigger action at control inputs makes the circuit tolerant of slower input rise and fall times. This device is fully specified for partial power-down applications using I . The I OFF OFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered down. This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications. 2. Features and benefits Automotive product qualification in accordance with AEC-Q100 (Grade 1) Specified from -40 C to +85 C and from -40 C to +125 C Supply voltage range from 2.3 V to 3.6 V High noise immunity Complies with JEDEC standard: JESD8-5 (2.3 V to 2.7 V) JESD8-B/JESD36 (2.7 V to 3.6 V) ESD protection: MIL-STD-883, method 3015 exceeds 2000 V HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 ) 5 switch connection between two ports Rail to rail switching on data I/O ports CMOS low power consumption Latch-up performance exceeds 250 mA per JESD78B Class I level A I circuitry provides partial Power-down mode operation OFF DHVQFN package with Side-Wettable Flanks enabling Automatic Optical Inspection (AOI) of solder joints 3. Ordering information Table 1. Ordering information Type number Package Temperature Name Description Version range 74CBTLV3245PW-Q100 -40 C to +125 C TSSOP20 plastic thin shrink small outline package SOT360-1 20 leads body width 4.4 mm 74CBTLV3245BQ-Q100 -40 C to +125 C DHVQFN20 plastic dual in-line compatible thermal SOT764-1 enhanced very thin quad flat package no leads 20 terminals body 2.5 4.5 0.85 mmNexperia 74CBTLV3245-Q100 8-bit bus switch with output enable 4. Functional diagram A1 A2 A3 A4 A5 A6 A7 A8 2 3 4 5 6 7 8 9 19 OE 18 17 16 15 14 13 12 11 B1 B2 B3 B4 B5 B6 B7 B8 001aan323 Fig. 1. Logic symbol nA nB OE 001aan324 Fig. 2. Logic diagram (one switch) 5. Pinning information 5.1. Pinning 74CBTLV3245-Q100 terminal 1 index area A1 2 19 OE A2 3 18 B1 A3 4 17 B2 A4 5 16 B3 74CBTLV3245-Q100 6 15 A5 B4 n.c. 1 20 V CC A6 7 14 B5 A1 2 19 OE A7 8 (1) 13 B6 GND A2 3 18 B1 A8 9 12 B7 A3 4 17 B2 A4 5 16 B3 A5 6 15 B4 aaa-022127 A6 7 14 B5 Transparent top view A7 8 13 B6 (1) This is not a ground pin. There is no electrical or A8 9 12 B7 mechanical requirement to solder the pad. In case GND 10 11 B8 soldered, the solder land should remain floating or aaa-022126 connected to GND. Fig. 3. Pin configuration SOT360-1 (TSSOP20) Fig. 4. Pin configuration SOT764-1 (DHVQFN20) 74CBTLV3245 Q100 All information provided in this document is subject to legal disclaimers. Nexperia B.V. 2020. All rights reserved Product data sheet Rev. 4 7 May 2020 2 / 15 GND 10 1 n.c. B8 11 20 V CC