74AUP2G17GM,115

74AUP2G17 Low-power dual Schmitt trigger Rev. 8 9 August 2021 Product data sheet 1. General description The 74AUP2G17 is a dual buffer with Schmitt-trigger inputs. This device ensures very low static and dynamic power consumption across the entire V range from 0.8 V to 3.6 V. This device is CC fully specified for partial power down applications using I . The I circuitry disables the output, OFF OFF preventing the potentially damaging backflow current through the device when it is powered down. 2. Features and benefits Wide supply voltage range from 0.8 V to 3.6 V CMOS low power dissipation High noise immunity Overvoltage tolerant inputs to 3.6 V Low noise overshoot and undershoot < 10 % of V CC I circuitry provides partial power-down mode operation OFF Latch-up performance exceeds 100 mA per JESD 78 Class II Level B Low static power consumption I = 0.9 A (maximum) CC Complies with JEDEC standards: JESD8-12 (0.8 V to 1.3 V) JESD8-11 (0.9 V to 1.65 V) JESD8-7 (1.2 V to 1.95 V) JESD8-5 (1.8 V to 2.7 V) JESD8C (2.7 V to 3.6 V) ESD protection: HBM JESD22-A114F Class 3A exceeds 5000 V MM JESD22-A115-A exceeds 200 V CDM JESD22-C101E exceeds 1000 V Multiple package options Specified from -40 C to +85 C and -40 C to +125 C 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74AUP2G17GW -40 C to +125 C SC-88 plastic surface-mounted package 6 leads SOT363 74AUP2G17GM -40 C to +125 C XSON6 plastic extremely thin small outline package no leads SOT886 6 terminals body 1 1.45 0.5 mm 74AUP2G17GN -40 C to +125 C XSON6 extremely thin small outline package no leads SOT1115 6 terminals body 0.9 1.0 0.35 mm 74AUP2G17GS -40 C to +125 C XSON6 extremely thin small outline package no leads SOT1202 6 terminals body 1.0 1.0 0.35 mmNexperia 74AUP2G17 Low-power dual Schmitt trigger 4. Marking Table 2. Marking Type number Marking code 1 74AUP2G17GW pV 74AUP2G17GM pV 74AUP2G17GN pV 74AUP2G17GS pV 1 The pin 1 indicator is located on the lower left corner of the device, below the marking code. 5. Functional diagram 1 6 1A 1Y 1 1A 1Y 6 3 2A 2Y 4 3 4 2A 2Y mnb066 mnb067 mnb068 Fig. 1. Logic symbol Fig. 2. IEC logic symbol Fig. 3. Logic diagram 6. Pinning information 6.1. Pinning 74AUP2G17 74AUP2G17 74AUP2G17 1A 1 6 1Y 1A 1 6 1Y 1A 1 6 1Y GND 2 5 V GND 2 5 V CC CC GND 2 5 V CC 2A 3 4 2Y 2A 3 4 2Y 2A 3 4 2Y 001aae790 001aab674 001aab675 Transparent top view Fig. 4. Pin configuration SOT363 Fig. 5. Pin configuration SOT886 Fig. 6. Pin configuration SOT1115 (SC-88) (XSON6) and SOT1202 (XSON6) 6.2. Pin description Table 3. Pin description Symbol Pin Description 1A 1 data input GND 2 ground (0 V) 2A 3 data input 2Y 4 data output V 5 supply voltage CC 1Y 6 data output 74AUP2G17 All information provided in this document is subject to legal disclaimers. Nexperia B.V. 2021. All rights reserved Product data sheet Rev. 8 9 August 2021 2 / 17