74AUP2G06GW

74AUP2G06 Low-power dual inverter with open-drain output Rev. 5 29 November 2012 Product data sheet 1. General description The 74AUP2G06 provides two inverting buffers with open-drain output. The output of the device is an open drain and can be connected to other open-drain outputs to implement active-LOW wired-OR or active-HIGH wired-AND functions. Schmitt-trigger action at all inputs makes the circuit tolerant to slower input rise and fall times across the entire V range from 0.8 V to 3.6 V. CC This device ensures a very low static and dynamic power consumption across the entire V range from 0.8 V to 3.6 V. CC This device is fully specified for partial Power-down applications using I . OFF The I circuitry disables the output, preventing the damaging backflow current through OFF the device when it is powered down. 2. Features and benefits Wide supply voltage range from 0.8 V to 3.6 V High noise immunity Complies with JEDEC standards: JESD8-12 (0.8 V to 1.3 V) JESD8-11 (0.9 V to 1.65 V) JESD8-7 (1.2 V to 1.95 V) JESD8-5 (1.8 V to 2.7 V) JESD8-B (2.7 V to 3.6 V) ESD protection: HBM JESD22-A114F Class 3A. Exceeds 5000 V MM JESD22-A115-A exceeds 200 V CDM JESD22-C101E exceeds 1000 V Low static power consumption I = 0.9 A (maximum) CC Latch-up performance exceeds 100 mA per JESD 78B Class II Inputs accept voltages up to 3.6 V Low noise overshoot and undershoot < 10 % of V CC I circuitry provides partial Power-down mode operation OFF Multiple package options Specified from 40 Cto+85 C and 40 Cto+125 C74AUP2G06 NXP Semiconductors Low-power dual inverter with open-drain output 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74AUP2G06GW 40 C to +125 C SC-88 plastic surface-mounted package 6 leads SOT363 74AUP2G06GM 40 C to +125 C XSON6 plastic extremely thin small outline package no leads SOT886 6 terminals body 1 1.45 0.5 mm 74AUP2G06GF 40 C to +125 C XSON6 plastic extremely thin small outline package no leads SOT891 6 terminals body 1 1 0.5 mm 74AUP2G06GN 40 C to +125 C XSON6 extremely thin small outline package no leads SOT1115 6 terminals body 0.9 1.0 0.35 mm 74AUP2G06GS 40 C to +125 C XSON6 extremely thin small outline package no leads SOT1202 6 terminals body 1.0 1.0 0.35 mm 4. Marking Table 2. Marking 1 Type number Marking code 74AUP2G06GW p6 74AUP2G06GM p6 74AUP2G06GF p6 74AUP2G06GN p6 74AUP2G06GS p6 1 The pin 1 indicator is located on the lower left corner of the device, below the marking code. 5. Functional diagram 1 1A 1Y 6 1 6 1A 1Y Y 3 2A 2Y 4 A 3 4 2A 2Y GND mnb095 mnb096 mna620 Fig 1. Logic symbol Fig 2. IEC logic symbol Fig 3. Logic diagram (one driver) 74AUP2G06 All information provided in this document is subject to legal disclaimers. NXP B.V. 2012. All rights reserved. Product data sheet Rev. 5 29 November 2012 2 of 18