74ALVCH162244DGG:1

74ALVCH162244 16-bit buffer/line driver with 30 termination resistor 3-State Rev. 3 16 January 2018 Product data sheet 1 General description The 74ALVCH162244 is a 16-bit non-inverting buffer/line driver with 3-state outputs. The device can be used as four 4-bit buffers, two 8-bit buffers or one 16-bit buffer. The 3-state outputs are controlled by the output enable inputs 1OE, 2OE, 3OE and 4OE. A HIGH on nOE causes the outputs to assume a high-impedance OFF-state. The 74ALVCH162244 is designed with 30 series resistors in both HIGH and LOW output states. The 74ALVCH162244 has active bus hold circuitry which is provided to hold unused or floating data inputs at a valid logic level. This feature eliminates the need for external pull-up or pull-down resistors. 2 Features and benefits Wide supply voltage range from 1.2 V to 3.6 V CMOS low power consumption MultiByte flow-through standard pin-out architecture Low inductance multiple V and GND pins for minimum noise and ground bounce CC Direct interface with TTL levels (2.7 V to 3.6 V) Bus hold on all data inputs Integrated 30 termination resistor Complies with JEDEC standards: JESD8-5 (2.3 V to 2.7 V) JESD8B/JESD36 (2.7 V to 3.6 V) ESD protection: HBM ANSI/ESDA/JEDEC JS-001 exceeds 2000 V CDM JESD22-C101E exceeds 1000 V 3 Ordering information Table 1.Ordering information Type number Package Temperature range Name Description Version 74ALVCH162244DGG 40 C to +85 C TSSOP48 plastic thin shrink small outline package SOT362-1 48 leads body width 6.1 mmNexperia 74ALVCH162244 16-bit buffer/line driver with 30 termination resistor 3-State 4 Functional diagram 47 2 36 13 1A0 1Y0 3A0 3Y0 46 3 35 14 1A1 3A1 1Y1 3Y1 1 1OE EN1 48 2OE EN2 44 5 33 16 25 1A2 3A2 1Y2 3Y2 3OE EN3 24 4OE EN4 43 6 32 17 47 2 1A3 1Y3 3A3 3Y3 1A0 1 1 1Y0 46 3 1A1 1Y1 1 25 44 5 1OE 3OE 1A2 1Y2 43 6 1A3 1Y3 41 8 2A0 1 2 2Y0 40 9 8 19 41 30 2A1 2Y1 2A0 2Y0 4A0 4Y0 38 11 2A2 2Y2 37 12 2A3 2Y3 40 9 29 20 36 13 2A1 4A1 3A0 1 3 3Y0 2Y1 4Y1 35 14 3A1 3Y1 33 16 38 11 27 22 3A2 3Y2 32 17 2A2 2Y2 4A2 4Y2 3A3 3Y3 30 19 4A0 1 4 4Y0 29 20 37 12 26 23 4A1 4Y1 2A3 2Y3 4A3 4Y3 27 22 4A2 4Y2 26 23 48 24 4A3 4Y3 2OE 4OE mna996 001aae231 Figure 1.Logic symbol Figure 2.IEC logic symbol V CC data input to internal circuit mna705 Figure 3.Bus hold circuit 74ALVCH162244 All information provided in this document is subject to legal disclaimers. Nexperia B.V. 2018. All rights reserved. Product data sheet Rev. 3 16 January 2018 2 / 14