74AHC32D,112

74AHC32 74AHCT32 Quad 2-input OR gate Rev. 5 5 June 2020 Product data sheet 1. General description The 74AHC32 74AHCT32 is a quad 2-input OR gate. Inputs are overvoltage tolerant. This feature allows the use of these devices as translators in mixed voltage environments. 2. Features and benefits Wide supply voltage range from 2.0 V to 5.5 V Input levels: For 74AHC32: CMOS level For 74AHCT32: TTL level Balanced propagation delays All inputs have Schmitt-trigger actions Overvoltage tolerant inputs to 5.5 V High noise immunity CMOS low power dissipation ESD protection: HBM EIA/JESD22-A114E exceeds 2000 V MM EIA/JESD22-A115-A exceeds 200 V CDM EIA/JESD22-C101C exceeds 1000 V Latch-up performance exceeds 100 mA per JESD 78 Class II Level A Multiple package options Specified from -40 C to +85 C and from -40 C to +125 C 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74AHC32D -40 C to +125 C SO14 plastic small outline package 14 leads SOT108-1 body width 3.9 mm 74AHCT32D 74AHC32PW -40 C to +125 C TSSOP14 plastic thin shrink small outline package 14 leads SOT402-1 body width 4.4 mm 74AHCT32PW 74AHC32BQ -40 C to +125 C DHVQFN14 plastic dual in-line compatible thermal SOT762-1 enhanced very thin quad flat package no leads 74AHCT32BQ 14 terminals body 2.5 3 0.85 mmNexperia 74AHC32 74AHCT32 Quad 2-input OR gate 4. Functional diagram 1 1 3 2 4 1 6 1 1A 1Y 3 5 2 1B 4 2A 2Y 6 9 5 2B 1 8 10 9 3A 3Y 8 10 3B 12 12 4A 1 4Y 11 11 13 4B 13 mna242 mna243 Fig. 1. Logic symbol Fig. 2. IEC logic symbol A Y B mna241 Fig. 3. Logic diagram (one gate) 5. Pinning information 5.1. Pinning 74AHC32 74AHCT32 terminal 1 index area 74AHC32 74AHCT32 2 13 1B 4B 1Y 3 12 4A 1A 1 14 V CC 2A 4 11 4Y 2 13 1B 4B 2B 5 (1) 10 3B GND 1Y 3 12 4A 2Y 6 9 3A 2A 4 11 4Y 5 10 001aad102 2B 3B Transparent top view 2Y 6 9 3A (1) This is not a ground pin. There is no electrical or GND 7 8 3Y mechanical requirement to solder the pad. In case 001aad101 soldered, the solder land should remain floating or connected to GND. Fig. 4. Pin configuration SOT108-1 (SO14) and SOT402-1 (TSSOP14) Fig. 5. Pin configuration SOT762-1 (DHVQFN14) 74AHC AHCT32 All information provided in this document is subject to legal disclaimers. Nexperia B.V. 2020. All rights reserved Product data sheet Rev. 5 5 June 2020 2 / 13 GND 7 1 1A 3Y 8 14 V CC