74LV164 8-bit serial-in/parallel-out shift register Rev. 4 9 December 2015 Product data sheet 1. General description The 74LV164 is a low-voltage, Si-gate CMOS device and is pin and function compatible with the 74HC164 and 74HCT164. The 74LV164 is an 8-bit edge-triggered shift register with serial data entry and an output from each of the eight stages. Data is entered serially through one of two inputs (DSA or DSB) and either input can be used as an active HIGH enable for data entry through the other input. Both inputs must be connected together or an unused input must be tied HIGH. Data shifts one place to the right on each LOW-to-HIGH transition of the clock input (CP) and enters into Q0, which is the logical AND-function of the two data inputs (DSA and DSB) that existed one set-up time prior to the rising clock edge. A LOW on the master reset input (MR) overrides all other inputs and clears the register asynchronously, forcing all outputs LOW. 2. Features and benefits Wide operating voltage: 1.0 V to 5.5 V Optimized for low-voltage applications: 1.0 V to 3.6 V Accepts TTL input levels between V = 2.7 V and V = 3.6 V CC CC Typical V (output ground bounce): < 0.8 V at V = 3.3 V and T = 25 C OLP CC amb Typical V (output V undershoot): > 2 V at V = 3.3 V and T = 25 C OHV OH CC amb Gated serial data inputs Asynchronous master reset ESD protection: HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-A exceeds 200 V Specified from 40 Cto+80 C and from 40 Cto+125 C.74LV164 NXP Semiconductors 8-bit serial-in/parallel-out shift register 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74LV164D 40 Cto+125 C SO14 plastic small outline package 14 leads SOT108-1 body width 3.9 mm 74LV164DB 40 Cto+125 C SSOP14 plastic shrink small outline package 14 leads SOT337-1 body width 5.3 mm 74LV164PW 40 Cto+125 C TSSOP14 plastic thin shrink small outline package 14 leads SOT402-1 body width 4.4 mm 74LV164BQ 40 Cto+125 C DHVQFN14 plastic dual in-line compatible thermal enhanced very SOT762-1 thin quad flat package no leads 14 terminals body 2.5 3 0.85 mm 4. Functional diagram & 5 05 DF D DD F Fig 1. Logic symbol Fig 2. IEC logic symbol 7 6(5, / %, 3 5 /1 ( / / , 2 7 8 7 5(*, 67(56+,) 4 4 DF D Fig 3. Functional diagram 74LV164 All information provided in this document is subject to legal disclaimers. NXP Semiconductors N.V. 2015. All rights reserved. Product data sheet Rev. 4 9 December 2015 2 of 18 4 4 4 4 4 4 05 &3 6% 6 4 4 4 &3 4 4 4 6% 4 6 4 65*