MT48LC8M16A2P-75 IT:G TR

128Mb: x4, x8, x16 SDRAM Features SDR SDRAM MT48LC32M4A2 8 Meg x 4 x 4 Banks MT48LC16M8A2 4 Meg x 8 x 4 Banks MT48LC8M16A2 2 Meg x 16 x 4 Banks Options Marking Features Configurations PC100- and PC133-compliant 32 Meg x 4 (8 Meg x 4 x 4 banks) 32M4 Fully synchronous all signals registered on positive 16 Meg x 8 (4 Meg x 8 x 4 banks) 16M8 edge of system clock 8 Meg x 16 (2 Meg x 16 x 4 banks) 8M16 Internal, pipelined operation column address can t Write recovery ( WR) be changed every clock cycle t WR = 2 CLK A2 Internal banks for hiding row access/precharge 1 Plastic package OCPL Programmable burst lengths (BL): 1, 2, 4, 8, or full 54-pin TSOP II (400 mil) TG page 54-pin TSOP II OCPL (400 mil) Pb- P Auto precharge, includes concurrent auto precharge free and auto refresh modes 2 60-ball FBGA (8mm x 16mm) FB Self refresh mode standard and low power 2 60-ball FBGA (8mm x 16mm) Pb-free BB 64ms, 4096-cycle (commercial and industrial) 3 54-ball VFBGA (8mm x 8mm) F4 16ms, 4096-cycle refresh (automotive) 3 54-ball VFBGA (8mm x 8mm) Pb-free B4 LVTTL-compatible inputs and outputs Timing cycle time Single 3.3V 0.3V power supply 7.5ns CL = 3 (PC133) -75 7.5ns CL = 2 (PC133) -7E 6.0ns CL = 3 (x16 only) -6A Self refresh Standard None Low power L Revision :G/:L Operating temperature range Commercial (0C to +70C) None 2 Industrial (40C to +85C) IT 2 Automotive (40C to +105C) AT 1. Off-center parting line. Notes: 2. Contact Micron for availability. 3. x16 only. Table 1: Key Timing Parameters CL = CAS (READ) latency Clock t t t t Speed Grade Frequency (MHz) Target RCD- RP-CL RCD (ns) RP (ns) CL (ns) -6A 167 3-3-3 18 18 18 -75 133 3-3-3 20 20 20 -7E 133 2-2-2 15 15 15 PDF: 09005aef8091e66d Micron Technology, Inc. reserves the right to change products or specifications without notice. 1 128Mb sdr.pdf - Rev. Q 1/12 EN 1999 Micron Technology, Inc. All rights reserved. Products and specifications discussed herein are subject to change by Micron without notice.128Mb: x4, x8, x16 SDRAM Features Table 2: Address Table Parameter 32 Meg x 4 16 Meg x 8 8 Meg x 16 Configuration 8 Meg x 4 x 4 banks 4 Meg x 8 x 4 banks 2 Meg x 16 x 4 banks Refresh count 4K 4K 4K Row addressing 4K A 11:0 4K A 11:0 4K A 11:0 Bank addressing 4 BA 1:0 4 BA 1:0 4 BA 1:0 Column 2K A 9:0 , A11 1K A 9:0 512 A 8:0 addressing Table 3: 128Mb SDR Part Numbering Part Numbers Architecture MT48LC32M4A2TG 32 Meg x 4 MT48LC32M4A2P 32 Meg x 4 MT48LC16M8A2TG 16 Meg x 8 MT48LC16M8A2P 16 Meg x 8 MT48LC16M8A2FB 16 Meg x 8 MT48LC16M8A2BB 16 Meg x 8 MT48LC8M16A2TG 8 Meg x 16 MT48LC8M16A2P 8 Meg x 16 MT48LC8M16A2B4 8 Meg x 16 MT48LC8M16A2F4 16 Meg x 16 Note: 1. FBGA Device Decoder: www.micron.com/decoder PDF: 09005aef8091e66d Micron Technology, Inc. reserves the right to change products or specifications without notice. 2 128Mb sdr.pdf - Rev. Q 1/12 EN 1999 Micron Technology, Inc. All rights reserved.