ZL30151 3-Input, 3-Output Any-to-Any Line Card PLL with Ultra-Low Jitter Product Brief August 2014 Ordering Information Features ZL30151LDG1 32 Pin QFN Trays Input clocks ZL30151LDF1 32 Pin QFN Tape and Reel Three inputs, two differential/CMOS, one CMOS Matte Tin Any input frequency from 1kHz to 650Hz Package size: 5 x 5 mm (1kHz to 300MHz for CMOS) Inputs continually monitored for activity and -40 C to +85 C frequency accuracy In 2xCMOS mode, the P and N pins can be Automatic or manual reference switching different frequencies (e.g. 125MHz and 25MHz) Per-output supply pin with CMOS output Low-bandwidth DPLL voltages from 1.5V to 3.3V Programmable bandwidth, 1Hz to 500Hz Precise output alignment circuitry and per- Attenuates jitter up to several UI output phase adjustment Per-output enable/disable and glitchless Free-run or holdover on loss of all inputs start/stop (stop high or low) Hitless reference switching General Features High-resolution holdover averaging Automatic self-configuration at power-up from Digitally controlled phase adjustment internal EEPROM up to four configurations pin-selectable Low-jitter Fractional-N APLL and 3 Outputs Numerically controlled oscillator mode Any output frequency from <1Hz to 650MHz Zero-delay mode with external feedback High-resolution fractional frequency conversion SPI or I2C processor Interface with 0ppm error Easy-to-use evaluation software Easy-to-configure, encapsulated design requires no external VCXO or loop filter Applications components Telecom line cards for SONET/SDH, PDH, Each output has independent dividers Synchronous Etherenet, Fibre Channel Output jitter is typically 0.17 to 0.28ps RMS Broadcast video equipment (12kHz-20MHz integration band) Frequency conversion and frequency synthesis in a wide variety of equipment types Outputs are CML or 2xCMOS, can interface to LVDS, LVPECL, HSTL, SSTL and HCSL IC1P, IC1N OC1P, OC1N HSDIV1 HSDIV1 DIV1 Input Block DPLL APLL VDDO1 Divider, Hitless Switching, 3.715-4.18GHz, IC2P, IC2N OC2P, OC2N HSDIV2 Monitor, Jitter Filtering, DIV2 Fractional-N Holdover Selector VDDO2 IC3P/GPIO3 OC3P, OC3N HSDIV3 HSDIV2 DIV3 VDDO3 Microprocessor Port (SPI or I2C Serial) XA xtal and HW Control and Status Pins driver 2 XB Figure 1 - Functional Block Diagram 1 Microsemi Corporation Copyright 2014. Microsemi Corporation. All Rights Reserved. RSTN AC0/GPIO0 AC1/GPIO1 TEST/GPIO2 IC3/GPIO3 IF0/CSN IF1/MISO SCL/SCLK SDA/MOSI ZL30151 Product Brief 1. Application Examples 19.44M, 25M, etc. From primary 2x 156.25MHz differential ZL30151 and backup 125MHz CMOS timing functions 25MHz CMOS Input clock monitoring, hitless switching, frequency conversion, XO and jitter attenuation if needed. Figure 2 - Telecom SyncE Line Card Application 27MHz or 27MHz or ZL30151 74.25MHz or 74.25MHz or 74.1758MHz 74.1758MHz Frequency conversion and optional jitter attenuation. Figure 3 - Broadcast Video Frequency Conversion Application 2. Detailed Features 2.1 Input Block Features Three input clocks, two differential or single-ended, one single-ended Input clocks can be any frequency from 1kHz up to 650MHz (differential) or 300MHz (single-ended) Supported telecom frequencies include PDH, SDH, Synchronous Ethernet, OTN, wireless Inputs constantly monitored by programmable activity monitors and frequency monitors Fast activity monitor can disqualify the selected reference after a few missing clock cycles Frequency measurement and monitoring with 1ppm resolution and accept/reject hysteresis Optional input clock invalidation on GPIO assertion to react to LOS signals from PHYs 2.2 DPLL Features Very high-resolution DPLL architecture State machine automatically transitions between free-run, locked, and holdover states Revertive or nonrevertive reference selection algorithm Programmable bandwidth from 1Hz to 500Hz Programmable phase-slope limiting Programmable frequency rate-of-change limiting Programmable tracking range (i.e. hold-in range) Truly hitless reference switching with <200ps output clock phase transient Output phase adjustment in 10ps steps High-resolution frequency and phase measurement Fast detection of input clock failure and transition to holdover mode Holdover frequency averaging with programmable averaging time and delay time Better than 100ppb initial holdover accuracy 2.3 APLL Features Very high-resolution fractional scaling (i.e. non-integer multiplication) Any-to-any frequency conversion with 0ppm error Two high-speed dividers (integers 4 to 15, half divides 4.5 to 7.5) Easy-to-configure, completely encapsulated design requires no external VCXO or loop filter components Bypass mode supports system testing 2 Microsemi Corporation