S25FS064S 64 Mbit (8 Mbyte), 1.8 V FS-S Flash Features Serial Peripheral Interface (SPI) with Multi-I/O Data Retention SPI Clock polarity and phase modes 0 and 3 20 Year Data Retention, minimum Double Data Rate (DDR) option Security Features Extended Addressing - 24 or 32-bit address options One Time Program (OTP) array of 1024 bytes Serial Command subset and footprint compatible with S25FL1-K, Block Protection: S25FL-P and S25FL-S SPI families Status Register bits to control protection against program or erase Multi I/O Command subset and footprint compatible with of a contiguous range of sectors. S25FL1-K S25FL-P and S25FL-S SPI families Hardware and software control options Read Advanced Sector Protection (ASP) Commands: Normal, Fast, Dual Output, Dual I/O, Quad Output, Individual sector protection controlled by boot code or password Quad I/O, DDR Quad I/O Option for password control of read access Modes: Burst Wrap, Continuous (XIP), QPI (QPI) Technology Serial Flash Discoverable Parameters (SFDP) and Common Flash Cypress 65 nm MirrorBit Technology with Eclipse Architecture Interface (CFI), for configuration information. Single Supply Voltage with CMOS I/O Program 1.7 V to 2.0 V 256 or 512 Bytes Page Programming buffer Temperature Range Program suspend and resume Industrial ( 40 C to +85 C) Automatic ECC -internal hardware Error Correction Code Industrial Plus ( 40 C to +105 C) generation with single bit error correction Extended ( 40 C to +125 C) Erase Automotive, AEC-Q100 Grade 3 (40 C to +85 C) Hybrid sector option Automotive, AEC-Q100 Grade 2 (40 C to +105 C) Physical set of eight 4KB sectors and one 32KB sector at the top Automotive, AEC-Q100 Grade 1 (40 C to +125 C) or bottom of address space with all remaining sectors of 64KB Packages (all Pb-free) Uniform sector option 8-lead SOIC 208 mil (SOC008) Uniform 64KB or 256KB blocks for software compatibility with LGA 5x6 mm (W9A008) higher density and future devices BGA-24 6 8 mm Erase suspend and resume 5 5 ball (FAB024) footprint Erase status evaluation Cycling Endurance 100,000 Program-Erase Cycles, minimum Logic Block Diagram CS SRAM SCK MirrorBit Array SI/IO0 SO/IO1 Y Decoders I/O Data Latch WP /IO2 Control Logic RESET /IO3 Data Path RESET Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 002-03631 Rev. *D Revised January 12, 2017 X DecodersS25FS064S Performance Summary Maximum Read Rates Command Clock Rate (MHz) MB/s Read 50 6.25 Fast Read 133 16.5 Dual Read 133 33 Quad Read 133 66 DDR Quad I/O Read 80 80 Typical Program and Erase Rates Operation KB/s Page Programming (256 Bytes page buffer) 712 Page Programming (512 Bytes page buffer) 1080 4 KBytes Physical Sector Erase (Hybrid Sector Option) 16 64 KBytes Sector Erase 275 256 KBytes Sector Erase 275 Typical Current Consumption, 40C to +85C Operation Current (mA) Serial Read 50 MHz 10 Serial Read 133 MHz 22 Quad Read 133 MHz 60 Quad DDR Read 80 MHz 70 Program 60 Erase 60 Standby 0.025 Deep Power Down 0.006 Document Number: 002-03631 Rev. *D Page 2 of 149