FUJITSU MICROELECTRONICS DS07-13703-7E DATA SHEET 16-bit Proprietary Microcontroller CMOS 2 F MC-16LX MB90540G/545G Series MB90F543G(S)/F546G(S)/F548G(S)/F549G(S)/549G(S)/V540G MB90543G(S)/547G(S)/548G(S)/F548GL(S) DESCRIPTION The MB90540G/545G series with FULL-CAN and Flash ROM is specially designed for automotive and industrial applications. Its main features are on-board CAN Interfaces (MB90540G series: 2 channels, MB90545G series: 1 channel) , which conform to CAN V2.0A and V2.0B specifications, supporting very flexible message buffer 2 scheme and so offering more functions than a normal full CAN approach. The instruction set by F MC-16LX CPU 2 core inherits an AT architecture of the F MC* family with additional instruction sets for high-level languages, extended addressing mode, enhanced multiplication/division instructions, and enhanced bit manipulation instruc- tions.The micro controller has a 32-bit accumulator for processing long word data.The MB90540G/545G series has peripheral resources of 8/10-bit A/D converters, UART (SCI) , extended I/O serial interfaces, 8/16-bit timer, I/O timer (input capture (ICU) , output compare (OCU) ) . 2 * : F MC is the abbreviation of FUJITSU Flexible Microcontroller. FEATURES Clock Embedded PLL clock multiplication circuit Operating clock (PLL clock) can be selected from : divided-by-2 of oscillation or one to four times the oscillation Minimum instruction execution time : 62.5 ns (operation at oscillation of 4 MHz, PLL four times multiplied : machine clock 16 MHz and at operating VCC = 5.0 V) Subsystem Clock : 32 kHz Instruction set to optimize controller applications Rich data types (bit, byte, word, long word) Rich addressing mode (23 types) Enhanced signed multiplication/division instruction and RETI instruction functions Enhanced precision calculation realized by the 32-bit accumulator (Continued) For the information for microcontroller supports, see the following web site. MB90540G/545G Series Instruction set designed for high level language (C language) and multi-task operations Adoption of system stack pointer Enhanced pointer indirect instructions Barrel shift instructions Program patch function (for two address pointers) Enhanced execution speed : 4-byte Instruction queue Enhanced interrupt function : 8 levels, 34 factors Automatic data transmission function independent of CPU operation 2 Extended intelligent I/O service function (EI OS) Embedded ROM size and types MASK ROM : 256 Kbytes / 64 Kbytes / 128 Kbytes Flash ROM : 128 Kbytes/256 Kbytes Embedded RAM size : 2 Kbytes/4 Kbytes/6 Kbytes/8 Kbytes (evaluation chip) Flash ROM Supports automatic programming, Embedded Algorithm Write/Erase/Erase-Suspend/Resume commands A flag indicating completion of the algorithm Hard-wired reset vector available in order to point to a fixed boot sector in Flash Memory Erase can be performed on each block Block protection with external programming voltage Low-power consumption (stand-by) mode Sleep mode (mode in which CPU operating clock is stopped) Stop mode (mode in which oscillation is stopped) CPU intermittent operation mode Watch mode Hardware stand-by mode Process 0.5 m CMOS technology I/O port General-purpose I/O ports : 81 ports Timer Watchdog timer : 1 channel 8/16-bit PPG timer : 8/16-bit 4 channels 16-bit reload timer : 2 channels 16-bit I/O timer 16-bit free-run timer : 1 channel Input capture : 8 channels Output compare : 4 channels Extended I/O serial interface : 1 channel UART0 With full-duplex double buffer (8-bit length) Clock asynchronized or clock synchronized (with start/stop bit) transmission can be selectively used. (Continued) 2 DS07-13703-7E