CY7C68001 EZ-USB SX2 High Speed USB Interface Device 1. Features 2. Applications USB 2.0-Certified Compliant DSL modems On the USB-IF Integrators List: Test ID Number 40000713 ATA interface Operates at High (480 Mbps) or Full (12 Mbps) Speed Memory card readers Supports Control Endpoint 0: Legacy conversion devices Used for handling USB device requests Cameras Supports Four Configurable Endpoints that share a 4-KB FIFO Space Scanners Endpoints 2, 4, 6, 8 for application-specific control and data Home PNA Standard 8- or 16-bit External Master Interface Wireless LAN Glueless interface to most standard microprocessors DSPs, ASICs, and FPGAs MP3 players Synchronous or Asynchronous interface Networking Integrated Phase-locked Loop (PLL) Printers 3.3V Operation, 5V Tolerant I/Os The Reference Designs section of the Cypress web site, www.cypress.com, provides additional tools for typical USB 56-pin SSOP and QFN Package applications. Each reference design comes complete with Complies with most Device Class Specifications firmware source code and object code, schematics, and documentation. 3. Logic Block Diagram SCL I2C Bus Controller (Master Only) SDA IFCLK* Read*, Write*, OE*, PKTEND*, CS 24 MHz PLL XTAL Interrupt , Ready SX2 Internal Logic Flags (3/4) Address (3) Control VCC FIFO 1.5K Data 8/16-Bit Data Bus CY Smart USB 4 KB DPLUS Data USB 2.0 XCVR DMINUS FS/HS Engine FIFO Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document : 38-08013 Rev. *J Revised July 07, 2009 + Feedback RESET WAKEUP*CY7C68001 5.3 Boot Methods 4. Introduction During the power up sequence, internal logic of the SX2 checks The EZ-USB SX2 USB interface device is designed to work 2 1,2 for the presence of an I C EEPROM. If it finds an EEPROM, with any external master, such as standard microprocessors, it boots off the EEPROM. When the presence of an EEPROM is DSPs, ASICs, and FPGAs to enable USB 2.0 support for any detected, the SX2 checks the value of first byte. If the first byte peripheral design. SX2 has a built in USB transceiver and Serial is found to be a 0xC4, the SX2 loads the next two bytes into the Interface Engine (SIE), along with a command decoder for IFCONFIG and POLAR registers, respectively. If the fourth byte sending and receiving USB data. The controller has four is also 0xC4, the SX2 enumerates using the descriptor in the endpoints that share a 4 KB FIFO space for maximum flexibility EEPROM, then signals to the external master when enumeration and throughput, and Control Endpoint 0. SX2 has three address is complete through an ENUMOK interrupt (See Interrupt pins and a selectable 8- or 16- bit data bus for command and data System on page 3.). If no EEPROM is detected, the SX2 relies input or output. on the external master for the descriptors. After this descriptor information is received from the external master, the SX2 Figure 4-1. Example USB System Diagram connects to the USB and enumerates. 5.3.1 EEPROM Organization W indows/USB Capable Host The valid sequence of bytes in the EEPROM are displayed in the following table. Table 5-1. Descriptor Length Set to 0x06: Default Enumeration USB Cable Byte Index Description 0 0xC4 USB Connection 1IFCONFIG 2POLAR Cypress EEPROM 3 0xC4 SX2 4 Descriptor Length (LSB):0x06 RAM/ROM 5 Descriptor Length (MSB): 0x00 Device CPU Application 6 VID (LSB) 7 VID (MSB) 8 PID (LSB) 9 PID (MSB) 10 DID (LSB) 5. Functional Overview 11 DID (MSB) 5.1 USB Signaling Speed Table 5-2. Descriptor Length Not Set to 0x06 SX2 operates at two of the three rates defined in the Universal Serial Bus Specification Revision 2.0, dated April 27, 2000: Byte Index Description Full speed, with a signaling bit rate of 12 Mbits/s 0 0xC4 1IFCONFIG High speed, with a signaling bit rate of 480 Mbits/s. 2POLAR SX2 does not support the low speed signaling rate of 1.5 Mbits/s. 3 0xC4 5.2 Buses 4 Descriptor Length (LSB) SX2 features: 5 Descriptor Length (MSB A selectable 8- or 16-bit bidirectional data bus 6 Descriptor 0 An address bus for selecting the FIFO or Command Interface. 7 Descriptor 1 8 Descriptor 2 Notes 1. Because there is no direct way to detect which EEPROM type (single or double address) is connected, SX2 uses the EEPROM address pins A2, A1, and A0 to determine whether to send out one or two bytes of address. Single-byte address EEPROMs (24LC01, etc.) should be strapped to address 000 and double-byte EEPROMs (24LC64, etc.) should be strapped to address 001. 2. The SCL and SDA pins must be pulled up for this detection method to work properly, even if an EEPROM is not connected. Typical pull up values are 2.2K10K Ohms. Document : 38-08013 Rev. *J Page 2 of 45 + Feedback