DEV-ADC34J22

Intelligent Systems Components North America Product Brief DEV-ADC34J22 The DEV-ADC34J22 is a four-channel, 50MSPS ADC Module designed to integrate with Alteras HSMC standard. The DEV-ADC34J22 features TIs new JESD204B compliant ADC34J22 Analog Digital Converter (ADC), with clocking conditioning using TIs LMK04828B jitter cleaner. It provides single-ended DC coupled inputs on two of the four channels through TIs THS4541 850MHz BW fully differential amplifier. Completely configurable via Alteras Cyclone V SOC FPGA The module offers six front panel SMA connectors: 1 EXT trigger, 1 EXT clock and 4 Analog Input Channels, and an on board 10MHz TCXO for stand -alone with embedded ARM Cortex clock generation, with a 100MHz VCXO used in conjunction with the LMK04828B for reference clock jitter cleaning. The ADC34J22 and the LMK04828B are A9 processors. completely configurable via Alteras Cyclone V SOC FPGA with embedded ARM Cortex A9 processors. The DEV-ADC34J22 supports a wide range of applications and offers two RF (AC coupled) channels and two Analog (DC coupled) channels. Board Highlights > Quad ADC Module supporting JESD204B, Subclass 0 & 1 > Features Texas instruments New ADC34J22 JESD204B ADC > Showcases JESD204B using Alteras Cyclone V family of FPGAs > DC coupled capability via Texas Instruments new THS4541 Fully Differential Amplifier (FDA) > Compatible with Arrows SOCKIT evaluation module > Follow up FMC module will be offered Q314 Order at parts.arrow.com Part No. DEV-ADC34J22 arrow.comDEV-ADC34J22 Product Brief Board Features > Texas Instruments ADC34J22 Analog to > On board TI LMK04828B Dual Loop > SPI control interfaces for both the Digital Converter ADC34J22 and LMK04828B devices > Clock Jitter Cleaner Reference oscillator - > 4 channel, 12bit, 50 MSPS, JESD204B 10MHz. TCXO > Reference design available for Arrows compliant ADC module SOCkit development board > 1st Loop VCO - 100MHz. VCXO > Two RF AC coupled input channels > VHDL design files including MTIs JESD > HSMC connector for interfacing with core instantiation > Two Analog DC coupled input channels Altera FPGA development boards Supports up to four JESD204B lanes > Module is configured at power-up by the > External clock input SOCs ARM processor > JESD204B Sub-class 0 & 1 compatible > External trigger input AC Coupled RF Front End RF Front End Features: > Transformer coupled single ended to differential conversion > Available on Channels 1 & 2 > RF Front End Specifications: Input range +/- 1.0V (2V p-p) > 0.5 - 200 MHz input bandwidth Applications Include: > IF Software Defined Radio (SDR) > Instrumentation > Radar > Portable Test Equipment Two Analog DC Coupled Input Channels Analog Front End Features: > Single Ended to Differential Amplifier with G=2 V/V In Person Available on Channels 3 & 4 Components 800 833 3557 > Analog Front End Specifications: > Input range +/- 0.5 V i.e. 1 Vp-p Online >DC - 15 MHz input bandwidth parts.arrow.com Applications Include: > Baseband Software Defined Radio (SDR) >Instrumentation > Medical Imaging 2014 Arrow Electronics, Inc. Arrow and the Arrow logo are registered trademarks of Arrow Electronics, Inc. All other product names and logos are trademarks of their respective manufacturers. IS-DEV-ADC34J22 08/14 CDS1.2