CMXDM7002A SURFACE MOUNT SILICON www.centralsemi.com DUAL N-CHANNEL DESCRIPTION: ENHANCEMENT-MODE The CENTRAL SEMICONDUCTOR CMXDM7002A MOSFET is special dual version of the 2N7002 enhancement- mode N-Channel MOSFET manufactured by the N-Channel DMOS Process, and designed for high speed pulsed amplifier and driver applications. This special dual transistor device offers low r and DS(ON) low V DS(ON). MARKING CODE: X02A SOT-26 CASE MAXIMUM RATINGS: (T =25C) SYMBOL UNITS A Drain-Source Voltage V 60 V DS Drain-Gate Voltage V 60 V DG Gate-Source Voltage V 40 V GS Continuous Drain Current I 280 mA D Continuous Source Current (Body Diode) I 280 mA S Maximum Pulsed Drain Current I 1.5 A DM Maximum Pulsed Source Current I 1.5 A SM Power Dissipation P 350 mW D Operating and Storage Junction Temperature T , T -65 to +150 C J stg Thermal Resistance 357 C/W JA ELECTRICAL CHARACTERISTICS PER TRANSISTOR: (T =25C unless otherwise noted) A SYMBOL TEST CONDITIONS MIN MAX UNITS I , I V =20V, V=0 100 nA GSSF GSSR GS DS I V =60V, V=0 1.0 A DSS DS GS I V =60V, V =0, T=125C 500 A DSS DS GS J I V =10V, V=10V 500 mA D(ON) GS DS BV V =0, I=10A 60 V DSS GS D V V =V , I=250A 1.0 2.5 V GS(th) DS GS D V V =10V, I=500mA 1.0 V DS(ON) GS D V V =5.0V, I =50mA 0.15 V DS(ON) GS D V V =0, I=400mA 1.2 V SD GS S r V =10V, I=500mA 2.0 DS(ON) GS D r V =10V, I =500mA, T=125C 3.5 DS(ON) GS D J r V =5.0V, I=50mA 3.0 DS(ON) GS D r V =5.0V, I =50mA, T=125C 5.0 DS(ON) GS D J g V =10V, I=200mA 80 mS FS DS D C V =25V, V =0, f=1.0MHz 5.0 pF rss DS GS C V =25V, V =0, f=1.0MHz 50 pF iss DS GS C V =25V, V =0, f=1.0MHz 25 pF oss DS GS R3 (9-February 2015)CMXDM7002A SURFACE MOUNT SILICON DUAL N-CHANNEL ENHANCEMENT-MODE MOSFET ELECTRICAL CHARACTERISTICS PER TRANSISTOR - Continued: (T =25C unless otherwise noted) A SYMBOL TEST CONDITIONS TYP MAX UNITS Q V =30V, V =4.5V, I=100mA 0.592 nC g(tot) DS GS D Q V =30V, V =4.5V, I=100mA 0.196 nC gs DS GS D Q V =30V, V =4.5V, I=100mA 0.148 nC gd DS GS D t , t V =30V, V =10V, I=200mA, on off DD GS D R =25, R=150 20 ns G L SOT-26 CASE - MECHANICAL OUTLINE PIN CONFIGURATION LEAD CODE: 1) Gate Q1 2) Source Q1 3) Drain Q2 4) Gate Q2 5) Source Q2 6) Drain Q1 MARKING CODE: X02A R3 (9-February 2015) www.centralsemi.com