SAM9261 Atmel SMART ARM-based Embedded MPU DATASHEET Description The Atmel SMART SAM9261 is a complete system-on-chip built around the ARM926EJ-S ARM Thumb processor with an extended DSP instruction set and Jazelle Java accelerator. It achieves 210 MIPS at 190 MHz. The SAM9261 is an optimized host processor for applications with an LCD display. Its integrated LCD controller supports BW and up to 16M color, active and passive LCD displays. The 160 Kbyte integrated SRAM can be configured as a frame buffer minimizing the impact for LCD refresh on the overall processor performance. The External Bus Interface incorporates controllers for synchronous DRAM (SDRAM) and Static memories and features specific interface circuitry for CompactFlash and NAND Flash. The SAM9261 integrates a ROM-based bootloader supporting code shadowing from, for example, external DataFlash into external SDRAM. The software controlled Power Management Controller (PMC) keeps system power consumption to a minimum by selectively enabling/disabling the processor and various peripherals and adjustment of the operating frequency. The SAM9261 also benefits from the integration of a wide range of debug features including JTAG-ICE, a dedicated UART debug channel (DBGU) and an embedded real time trace. This enables the development and debug of all applications, especially those with real-time constraints. Atmel-6062O-ATARM-SAM9261-Datasheet 21-Jun-16Features ARM926EJ-S ARM ThumbProcessor DSP Instruction Extensions ARM Jazelle Technology for Java Acceleration 16 Kbyte Data Cache, 16 Kbyte Instruction Cache, Write Buffer 210 MIPS at 190 MHz Memory Management Unit EmbeddedICE , Debug Communication Channel Support Mid-level implementation Embedded Trace Macrocell (ETM ) Additional Embedded Memories 32 Kbytes of Internal ROM, Single-cycle Access at Maximum Bus Speed 160 Kbytes of Internal SRAM, Single-cycle Access at Maximum Processor or Bus Speed External Bus Interface (EBI) Supports SDRAM, Static Memory, NAND Flash and CompactFlash LCD Controller Supports Passive or Active Displays Up to 16 bits per Pixel in STN Color Mode Up to 16M Colors in TFT Mode (24-bit per Pixel), Resolution up to 2048 x 2048 USB 2.0 Full Speed (12 Mbits per second) Host Double Port: Dual On-chip Transceivers, Integrated FIFOs and Dedicated DMA Channels Device Port: On-chip Transceiver, 2 Kbyte Configurable Integrated FIFOs Bus Matrix Handles Five Masters and Five Slaves Boot Mode Select Option Remap Command Fully Featured System Controller (SYSC) for Efficient System Management, including Reset Controller, Shutdown Controller, Four 32-bit Battery Backup Registers for a Total of 16 Bytes Clock Generator and Power Management Controller Advanced Interrupt Controller and Debug Unit Periodic Interval Timer, Watchdog Timer and Real-time Timer Three 32-bit PIO Controllers Reset Controller (RSTC) Based on Power-on Reset Cells, Reset Source Identification and Reset Output Control Shutdown Controller (SHDWC) Programmable Shutdown Pin Control and Wakeup Circuitry Clock Generator (CKGR) 32.768 kHz Low-power Oscillator on Battery Backup Power Supply, Providing a Permanent Slow Clock 3 to 20 MHz On-chip Oscillator and two PLLs Power Management Controller (PMC) Very Slow Clock Operating Mode, Software Programmable Power Optimization Capabilities Four Programmable External Clock Signals Advanced Interrupt Controller (AIC) Individually Maskable, Eight-level Priority, Vectored Interrupt Sources Three External Interrupt Sources and One Fast Interrupt Source, Spurious Interrupt Protected 2 SAM9261 DATASHEET Atmel-6062O-ATARM-SAM9261-Datasheet 21-Jun-16