MAX1005 19-1291 Rev 0 9/97 IF Undersampler General Description Features The MAX1005 is a combined digitizer and reconstruc- Differential-Input, 5-Bit ADC tion integrated circuit designed to work in systems that Differential-Output, 7-Bit DAC demodulate and modulate communications signals. It integrates IF undersampling and signal synthesis func- 15Msps Min Conversion Rate tions into a single, low-power circuit. Its analog-to- 25MHz -1dB Full-Power Bandwidth digital converter (ADC) is used to directly sample or undersample a downconverted RF signal, while its 44dB SFDR for ADC digital-to-analog converter (DAC) recreates the IF sub- 39dB at 10.7MHz SFDR (Imaged) for DAC carrier and transmission data. The MAX1005s ADC is Internal Voltage Reference ideal for undersampling applications, due to the analog input amplifiers wide (15MHz) bandwidth. The DAC Parallel Logic Interface has very low glitch energy, which minimizes the trans- mission of unwanted spurious signals. An on-chip Single-Supply Operation (+2.7V to +5.5V) reference provides for low-noise ADC and DAC conver- 0.1A Low-Power Shutdown Mode sions. The MAX1005 provides a high level of signal integrity from a low power budget. It operates from a single power supply, or from separate analog and digital sup- Ordering Information plies with independent voltages ranging from +2.7V to +5.5V. The MAX1005 can operate with an unregulated PART TEMP. RANGE PIN-PACKAGE analog supply of 5.5V and a regulated digital supply MAX1005CEE 0C to +70C 16 QSOP down to 2.7V. This flexible power-supply operation MAX1005EEE -40C to +85C 16 QSOP saves additional power in complex digital systems. The MAX1005 has three operating modes: transmit (DAC active), receive (ADC active), and shutdown (ADC and DAC inactive). In shutdown mode, the total Pin Configuration supply current drops below 1A. The device requires only 2.4s to wake up from shutdown mode. The MAX1005 is ideal for hand-held, as well as base-station applications. It is available in a tiny 16-pin QSOP pack- TOP VIEW age specified for operation over both the commercial and extended temperature ranges. VCCD 1 16 CLK DGND 2 15 D0 Applications RXEN 14 D1 3 PWT1900 AIO+ 4 MAX1005 13 D2 PHS/P AIO- 5 12 D3 Wireless Loops TXEN 6 11 D4 PCS/N AGND 7 10 D5 VCCA 8 9 D6 QSOP Functional Diagram appears at end of data sheet. Maxim Integrated Products 1 For free samples & the latest literature: IF Undersampler ABSOLUTE MAXIMUM RATINGS VCCA to AGND ........................................................-0.3V, +6.0V Power Dissipation (T = +70C) A VCCD to DGND........................................................-0.3V, +6.0V QSOP (derate 5.90mW/C above 70C) ......................470mW VCCA to VCCD ...................................................................6.3V Operating Temperature Ranges Digital I/O Pins (D0D6, CLK, RXEN, TXEN) MAX1005CEE .....................................................0C to +70C to DGND .................................-0.3V to (VCCD + 0.3V) or 6.0V MAX1005EEE...................................................-40C to +85C (whichever is smaller) Storage Temperature Range .............................-65C to +150C Analog I/O Pins (AIO+, AIO-) Lead Temperature (soldering, <10sec)...........................+300C to AGND................................(VCCA - 1.5V) to (VCCA + 0.3V) AGND to DGND........................................................-0.3V, +0.3V Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (VCCA = VCCD = 3.0V, f = 15MHz, R = , T = T to T , unless otherwise noted.) CLK L A MIN MAX PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS TRANSMIT DAC DC ACCURACY (Note 1) Resolution N 7 Bits Integral Nonlinearity INL 0.2 1 LSB Differential Nonlinearity DNL 0.2 1 LSB Offset Error 1 LSB Transmit Full-Scale Output Voltage V 736 800 864 mVp-p OUT TRANSMIT DAC DYNAMIC PERFORMANCE (T = +25C) (Note 2) A VCCA = VCCD = 3.0V 28 39 Spurious-Free Dynamic Range SFDR (Note 3) dBc VCCA = VCCD = 2.7V to 5.5V 39 Total Harmonic Distortion plus THD+N (Note 4) VCCA = VCCD = 3.0V -28 dBc Noise Wakeup Time Exiting Shutdown t 0.7 2.4 s WAKE Clock Feedthrough (Note 5) -50 dBc CLK DAC Latency (Notes 6, 7) 0.5 period VCC (A or D or both) = 3.0V 100mVp-p at Power-Supply Rejection PSR 67 dB 100kHz TRANSMIT ADC DC ACCURACY (Note 8) Resolution N 5 Bits Integral Nonlinearity INL 0.2 LSB Differential Nonlinearity DNL 0.2 LSB Offset Error AIO+ = AIO- 2 LSB Full-Scale Input Range V 368 400 432 mV IN RECEIVE ADC DYNAMIC PERFORMANCE (T = +25C) (Note 8) A VCCA = VCCD = 3.0V -42 -24 Total Harmonic Distortion THD (Notes 9, 10) dB VCCA = VCCD = 2.7V to 5.5V -42 VCCA = VCCD = 3.0V 24 44 Spurious-Free Dynamic Range SFDR (Note 9) dB VCCA = VCCD = 2.7V to 5.5V 44 VCCA = VCCD = 3.0V 4.5 4.9 Effective Number of Bits ENOB (Note 9) Bits VCCA = VCCD = 2.7V to 5.5V 4.9 2 MAX1005