DC2610A-A Analog Devices

LTC6953 Ultralow Jitter, 4.5GHz Clock Distributor with 11 Outputs and JESD204B/JESD204C Support FEATURES DESCRIPTION n JESD204B/C, Subclass 1 SYSREF Signal Generation The LTC 6953 is a high performance, ultralow jitter, n Additive Output Jitter < 6fs (Integration JESD204B/C clock distribution IC. The LTC6953s eleven RMS BW=12kHz to 20MHz, f = 4.5GHz) outputs can be configured as up to five JESD204B/C n Additive Output Jitter 65fs (ADC SNR Method) subclass 1 device clock/SYSREF pairs plus one general RMS n EZSync, ParallelSync Multichip Synchronization purpose output, or simply eleven general purpose clock n Eleven Independent, Low Noise Outputs with outputs for non-JESD204B/C applications. Each output Programmable Coarse Digital and Fine Analog Delays has its own individually programmable frequency divider n Flexible Outputs Can Serve as Either a Device Clock and output driver. All outputs can also be synchronized or SYSREF Signal and set to precise phase alignment using individual coarse n LTC6952Wizard Software Design Tool Support half cycle digital delays and fine analog time delays. n 40C to 125C Operating Junction Temperature Range For applications requiring more than eleven total out- puts, multiple LTC6953s can be connected together with APPLICATIONS LTC6952s and LTC6955s using the EZSync or ParallelSync synchronization protocols. n High Performance Data Converter Clocking All registered trademarks and trademarks are the property of their respective owners. Protected n Wireless Infrastructure by U.S. patents, including 8319551 and 8819472. n Test and Measurement TYPICAL APPLICATION Cumulative Phase Noise, Low Cost, Eleven Output JESD204B/C Solution LTC6946 Driving LTC6953 100 3.3V 3.3V 15 4.5GHz 5V 3.3V 57nF + + + + 500MHz V V V V IN REF D OUT 110 30.9 + + + + + + V V V V V V 68nH 68nH OUT0 15.625MHz ADC SYSREF VCO CP REF0 REF D RF 4.7nF OUT1 500MHz ADC CLOCK 120 100pF CP + + OUT2 15.625MHz ADC SYSREF TB RF IN OUT3 500MHz ADC CLOCK 130 2.2F CM A 160 100pF OUT4 15.625MHz FPGA SYSREF CM B RF IN OUT5 125MHz FPGA CLOCK 140 CM C OUT6 TUNE LTC6953 150 TOTAL COMBINED OUT7 15.625MHz DAC SYSREF 1F RMS JITTER = 150fs OUT8 4.5GHz DAC CLOCK LTC6946 RMS JITTER = 135fs + LTC6946-2 CS 160 REF LTC6963 RMS JITTER = 65fs OUT9 15.625MHz DAC SYSREF SCLK 49.9 EQUIVALENT ADC SNR METHOD OUT10 4.5GHz DAC CLOCK REF 170 1F SPI BUS SDI OUTPUT 1k 10k 100k 1M 10M 40M CS TERMINATION DETAIL 1F OFFSET FREQUENCY (Hz) 100 SDO 0.1F 6953 TAO1b SCLK BB + STAT OUTx SPI BUS SDI 1F 100 0.1F + SDO MUTE 3.3V EZS SRQ OUTx STAT REFO EZS SRQ CRYSTEK CCHD-575-25-100 6953 TA01a REGISTER VALUES: TO SYNC OUTPUTS: 100MHz REF OSC LTC6952Wizard FILE: LTC6946 LTC6953 EZSync TOGGLE LTC6953 SSYNC PLLWizard FILE: LTC6946 LTC6953 EZSync REGISTER BIT Rev. A 1 Document Feedback For more information www.analog.com PHASE NOISE (dBc/Hz)LTC6953 TABLE OF CONTENTS Features ............................................................................................................................ 1 Applications ....................................................................................................................... 1 Typical Application ............................................................................................................... 1 Description......................................................................................................................... 1 Absolute Maximum Ratings ..................................................................................................... 4 Order Information ................................................................................................................. 4 Electrical Characteristics ........................................................................................................ 4 Pin Configuration ................................................................................................................. 4 Typical Performance Characteristics .......................................................................................... 8 Pin Functions .....................................................................................................................11 Block Diagram ....................................................................................................................12 Timing Diagrams ................................................................................................................13 Operation..........................................................................................................................14 INPUT BUFFER ..................................................................................................................................................... 14 Input Peak Detector .......................................................................................................................................... 14 OUTPUT DIVIDERS (M0 TO M10) ........................................................................................................................ 14 DIGITAL OUTPUT DELAYS (DDEL0 TO DDEL10) .................................................................................................. 15 ANALOG OUTPUT DELAYS (ADEL0 TO ADEL10) .................................................................................................. 15 CML OUTPUT BUFFERS (OUT0 TO OUT10) .......................................................................................................... 15 OUTPUT SYNCHRONIZATION AND SYSREF GENERATION .................................................................................. 16 EZS SRQ Input Buffer ...................................................................................................................................... 16 Synchronization Overview ................................................................................................................................ 16 SYSREF Generation Overview .......................................................................................................................... 17 Multichip Synchronization and SYSREF Generation ......................................................................................... 17 EZSync Multichip .............................................................................................................................................. 19 ParallelSync ...................................................................................................................................................... 20 Power Savings in SYSREF Generation Mode .................................................................................................... 21 SERIAL PORT ....................................................................................................................................................... 23 Communication Sequence ................................................................................................................................ 23 Single Byte Transfers ........................................................................................................................................ 23 Multiple Byte Transfers ..................................................................................................................................... 24 Multidrop Configuration ................................................................................................................................... 25 Serial Port Registers ......................................................................................................................................... 25 STAT Output ..................................................................................................................................................... 29 Block Power-Down Control ............................................................................................................................... 29 Applications Information .......................................................................................................30 INTRODUCTION .................................................................................................................................................... 30 OUTPUT FREQUENCY ........................................................................................................................................... 30 DIGITAL AND ANALOG OUTPUT DELAYS ............................................................................................................. 30 INPUT BUFFER ..................................................................................................................................................... 31 EZS SRQ INPUT ................................................................................................................................................... 32 JESD204B/C DESIGN EXAMPLE USING EZSync STANDALONE ........................................................................... 33 Input Assumptions ........................................................................................................................................... 33 Design Procedure ............................................................................................................................................. 33 Rev. A 2 For more information www.analog.com