12-Bit High Speed Multiplying a D/A Converter DAC312 FEATURES PIN CONNECTIONS Differential Nonlinearity: 61/2 LSB 20-Pin Hermetic DIP (R-Suffix), Nonlinearity: 0.05% 20-Pin Plastic DIP (P-Suffix), Fast Settling Time: 250 ns 20-Pin SOL (S-Suffix) High Compliance: 5 V to +10 V Differential Outputs: 0 to 4 mA Guaranteed Monotonicity: 12 Bits Low Full-Scale Tempco: 10 ppm/8C Circuit Interface to TTL, CMOS, ECL, PMOS/NMOS Low Power Consumption: 225 mW Industry Standard AM6012 Pinout Available In Die Form GENERAL DESCRIPTION The DAC312 series of 12-bit multiplying digital-to-analog con- verters provide high speed with guaranteed performance to 0.012% differential nonlinearity over the full commercial oper- ating temperature range. High compliance and low drift characteristics (as low as 10 ppm/C) are also features of the DAC312 along with an ex- The DAC312 combines a 9-bit master D/A converter with a cellent power supply rejection ratio of .001% FS/%V. Oper- 3-bit (MSBs) segment generator to form an accurate 12-bit D/A ating over a power supply range of +5/11 V to 18 V the converter at low cost. This technique guarantees a very uniform device consumes 225 mW at the lower supply voltages with an step size (up to 1/2 LSB from the ideal), monotonicity to absolute maximum dissipation of 375 mW at the higher supply 12-bits and integral nonlinearity to 0.05% at its differential cur- levels. rent outputs. In order to provide the same performance with a 12-bit R-2R ladder design, an integral nonlinearity over tem- With their guaranteed specifications, single chip reliability and perature of 1/2 LSB (0.012%) would be required. low cost, the DAC312 device makes excellent building blocks for A/D converters, data acquisition systems, video display driv- The 250 ns settling time with low glitch energy and low power ers, programmable test equipment and other applications where consumption are achieved by careful attention to the circuit de- low power consumption and complete input/output versatility sign and stringent process controls. Direct interface with all are required. popular logic families is achieved through the logic threshold terminal. FUNCTIONAL BLOCK DIAGRAM REV. C Information furnished by Analog Devices is believed to be accurate and Analog Devices, Inc., 1996 reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 617/329-4700 Fax: 617/326-8703DAC312SPECIFICATIONS ( V = 615 V, I = 1.0 mA, 08C T +708C for DAC312E and 408C T +858C S REF A A for DAC312F, DAC312H, unless otherwise noted. Output characteristics refer to both I and I .) ELECTRICAL CHARACTERISTICS OUT OUT DAC312E DAC312F DAC312H Parameter Symbol Conditions Min Typ Max Min Typ Max Min Typ Max Units Resolution 12 12 12 Bits Monotonicity 12 12 12 Bits Differential Nonlinearity DNL Deviation from Ideal 0.0125 0.0250 0.0250 %FS 2 Step Size 0.5 1 1 LSB Nonlinearity INL Deviation from Ideal 0.05 0.05 0.05 %FS 1 Straight Line Full-Scale Current I V = 10 V FS REF 2 R = R = 10 k 3.967 3.999 4.031 3.935 3.999 4.063 3.935 3.999 4.063 mA 14 15 Full-Scale Tempco TCI 5 20 10 40 80 ppm/C FS 0.005 0.002 0.001 0.004 0.008 %FS/C Output Voltage Compliance V DNL Specification Guaran- OC teed over Compliance Range 5 +10 5 +10 5 +10 V Full-Scale Symmetry I I I 0.4 1 0.4 2 0.4 2 A FSS FS FS Zero-Scale Current I 0.10 0.10 0.10 A ZS Settling Time t To 1/2 LSB, All Bits S 1 Switched ON or OFF 250 500 250 500 250 500 ns Propagation DelayAll Bits t All Bits Switched 50% Point 25 50 25 50 25 50 ns PLH t Logic Swing to 50% Point 25 50 25 50 25 50 ns PHL 1 Output Output Resistance R >10 >10 >10 M O Output Capacitance C 20 20 20 pF OUT Logic Input Levels 0 V V = GND 0.8 0.8 0.8 V IL LC Levels 1 V V = GND 2 2 2 V IH LC Logic Input Current I V = 5 to +18 V 40 40 40 A IN IN Logic Input Swing V 5 +18 5 +18 5 +18 V IS Reference Bias Current I 0 0.5 2 0 0.5 2 0 0.5 2 A 15 Reference Input 1 Slew Rate dl/dt R = 800 , C = 0 pF 4 8 48 48 mA/s 14(eq) C Power Supply Sensitivity PSSI V+ = +13.5 V to +16.5 V, FS+ V = 15 V 0.0005 0.001 0.0005 0.001 0.0005 0.001 %FS/%V PSSI V = 13.5 V to 16.5 V, FS V+ = +15 V 0.00025 0.001 0.00025 0.001 0.00025 0.001 %FS/%V Power Supply Range V+ V = 0 V 4.5 18 4.5 18 4.5 18 V OUT V V = 0 V 18 10.8 18 10.8 18 10.8 V OUT Power Supply Current I+ V+ = +5 V, V = 15 V 3.3 7 3.3 7 3.3 7 mA I V+ = +15 V, V = 15 V 13.9 18 13.9 18 13 9 18 mA I+ V+ = +5 V, V = 15 V 3.9 7 3.9 7 3.9 7 mA I V+ = +15 V, V = 15 V 13.9 18 13.9 18 13.9 18 mA Power Dissipation P V+ = +5 V, V = 15 V 225 305 225 305 225 305 mW d V+ = +15 V, V = 15 V 267 375 267 375 267 375 mW TYPICAL ELECTRICAL CHARACTERISTICS 258C V = 615 V, and I = 1.0 mA, unless otherwise noted. Output S REF characteristics refer to both I and I . OUT OUT DAC312N DAC312G Parameter Symbol Conditions Typical Typical Units Reference Input Slew Rate dl/dt 8 8 mA/s Propagation Delay t , t Any Bit 25 25 ns PLH PHL Settling Time t To 1/2 LSB, All S Bits Switched ON 250 250 ns or OFF. Full-Scale TC 10 10 ppm/C IFS 2 REV. C