Quad ADC, Dual DAC, Low Latency, Low Power Codec Data Sheet ADAU1372 FEATURES APPLICATIONS Low latency, 24-bit ADCs and DACs Handsets, headsets, and headphones 102 dB SNR (through PGA and ADC with A-weighted filter) Bluetooth handsets, headsets, and headphones 107 dB dynamic range (through DAC and headphone with Personal navigation devices A-weighted filter) Digital still and video cameras Serial port sample rates from 8 kHz to 192 kHz GENERAL DESCRIPTION 4 single-ended analog inputs, configurable as microphone or The ADAU1372 is a codec with four inputs and two outputs, which line inputs incorporates asynchronous sample rate converters. Optimized Dual stereo digital microphone inputs for low latency and low power, the ADAU1372 is ideal for headsets, Stereo analog audio output, single-ended or differential, handsets, and headphones. The ADAU1372 has built-in program- configurable as either line output or headphone driver mable gain amplifiers (PGAs) thus, with the addition of just a PLL supporting any input clock rate from 8 MHz to 27 MHz few passive components and a crystal, the ADAU1372 provides Full-duplex, asynchronous sample rate converters (ASRCs) a solution for headset audio needs, microphone preamplifiers, Power supplies ADCs, DACs, headphone amplifiers, and serial ports for Analog and digital input/output of 1.8 V to 3.3 V connections to an external DSP. Low power (15.5 mW) 2 I C and SPI control interfaces for flexibility Note that throughout this data sheet, multifunction pins, such as 5 multipurpose pins supporting dual stereo digital SCL/SCLK, are referred to either by the entire pin name or by a microphone inputs, mute, push-button volume controls single function of the pin, for example, SCLK, when only that function is relevant. FUNCTIONAL BLOCK DIAGRAM MICBIAS0 MICROPHONE POWER LDO BIAS GENERATORS ADC SDATA1/CLKOUT/MP6 MICBIAS1 ADAU1372 MANAGEMENT REGULATOR CLOCK PLL XTALI/MCLKIN OSCILLATOR AIN0REF PGA XTALO AIN0 - ADC DECIMATOR AIN1REF HPOUTLP/LOUTLP - PGA AIN1 DACs - ADC HPOUTLN/LOUTLN INPUT/OUTPUT DECIMATOR SIGNAL ROUTING DMIC0 1/MP4 DIGITAL MICROPHONE DMIC2 3/MP5 INPUTS HPOUTRP/LOUTRP - DACs HPOUTRN/LOUTRN AIN2REF DECIMATOR PGA AIN2 - ADC BIDIRECTIONAL ASRCS AIN3REF DECIMATOR SERIAL I/O PORT PGA 2 I C/SPI CONTROL AIN3 - ADC INTERFACE CM Figure 1. Rev. 0 Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 2014 Analog Devices, Inc. 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Technical Support www.analog.com DGND DGND AGND AGND AGND PD BCLK DVDD LRCLK REG OUT DAC SDATA/MP0 AVDD ADC SDATA0/MP1 AVDD AVDD IOVDD ADDR0/SS ADDR1/MOSI SCL/SCLK SDA/MISO 12702-001ADAU1372 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Push-Button Volume Controls ................................................. 35 Applications ....................................................................................... 1 Mute ............................................................................................. 35 General Description ......................................................................... 1 Talkthrough Mode ..................................................................... 35 Functional Block Diagram .............................................................. 1 Serial Data Input/Output Ports .................................................... 36 Revision History ............................................................................... 3 Serial Port Initialization ............................................................ 36 Specif icat ions ..................................................................................... 4 Tristating Unused Channels...................................................... 37 Analog Performance Specifications ........................................... 4 Applications Information .............................................................. 39 Crystal Amplifier Specifications ................................................. 7 Power Supply Bypass Capacitors .............................................. 39 Digital Input/Output Specifications........................................... 8 Layout .......................................................................................... 39 Power Supply Specifications........................................................ 8 Grounding ................................................................................... 39 Typical Power Consumption ....................................................... 9 Exposed Pad PCB Design ......................................................... 39 Digital Filters ................................................................................. 9 System Block Diagram ............................................................... 40 Digital Timing Specifications ................................................... 10 Register Summary: Low Latency Codec ..................................... 41 Absolute Maximum Ratings .......................................................... 13 Register Details: Low Latency Codec .......................................... 43 Thermal Resistance .................................................................... 13 Clock Control Register .............................................................. 43 ESD Caution ................................................................................ 13 PLL Denominator MSB Register .............................................. 44 Pin Configuration and Function Descriptions ........................... 14 PLL Denominator LSB Register ............................................... 44 Typical Performance Characteristics ........................................... 17 PLL Numerator MSB Register .................................................. 44 Theory of Operation ...................................................................... 24 PLL Numerator LSB Register .................................................... 44 System Clocking and Power-Up ................................................... 25 PLL Integer Setting Register ..................................................... 45 Initialization ................................................................................ 25 PLL Lock Flag Register .............................................................. 46 Clock Initialization ..................................................................... 25 CLKOUT Setting Selection Register ........................................ 46 PLL ............................................................................................... 25 Regulator Control Register ....................................................... 47 Clock Output ............................................................................... 26 DAC Input Select Register ........................................................ 47 Power Sequencing ...................................................................... 26 Serial Data Output 0/Serial Data Output 1 Input Select Register ........................................................................................ 48 Signal Routing ................................................................................. 27 Serial Data Output 2/Serial Data Output 3 Input Select Input Signal Paths ........................................................................... 28 Register ........................................................................................ 49 Analog Inputs .............................................................................. 28 Serial Data Output 4/Serial Data Output 5 Input Select Digital Microphone Input ......................................................... 29 Register ........................................................................................ 50 Analog-to-Digital Converters ................................................... 29 Serial Data Output 6/Serial Data Output 7 Input Select Output Signal Paths ........................................................................ 30 Register ........................................................................................ 51 Analog Outputs........................................................................... 30 ADC SDATA0/ADC SDATA1 Channel Select Register ..... 53 Digital-to-Analog Converters ................................................... 30 Output ASRC0/Output ASRC1 Source Register .................... 53 Asynchronous Sample Rate Converters .................................. 30 Output ASRC2/Output ASRC3 Source Register .................... 54 Control Port ..................................................................................... 31 Input ASRC Channel Select Register ....................................... 56 Burst Mode Communication .................................................... 31 ADC Control 0 Register ............................................................ 56 2 I C Port ........................................................................................ 31 ADC Control 1 Register ............................................................ 57 SPI Port ........................................................................................ 34 ADC Control 2 Register ............................................................ 58 Burst Mode Communication .................................................... 34 ADC Control 3 Register ............................................................ 59 Multipurpose Pins .......................................................................... 35 ADC0 Volume Control Register .............................................. 60 Rev. 0 Page 2 of 92