ADATE318BCPZ

600 MHz Dual Integrated DCL with PPMU, VHH Drive Capability, Level Setting DACs, and On-Chip Calibration Engine Data Sheet ADATE318 FEATURES GENERAL DESCRIPTION 600 MHz/1200 Mbps data rate The ADATE318 is a complete, single-chip ATE solution that 3-level driver with high-Z and reflection clamps performs the pin electronics functions of driver, comparator, Window and differential comparators and active load (DCL), four quadrant, per pin, parametric 25 mA active load measurement unit (PPMU). It has VHH drive capability per Per pin PPMU with 2.0 V to +6.5 V range chip to support flash memory testing applications and integ- Low leakage mode (typically 4 nA) rated 16-bit DACs with an on-chip calibration engine to Integrated 16-bit DACs with offset and gain correction provide all necessary dc levels for operation of the part. High speed operating voltage range: 1.5 V to +6.5 V The driver features three active states: data high, data low, and Dedicated VHH output pin range: 0.0 V to 13.5 V terminate mode, as well as a high impedance inhibit state. The 1.1 W power dissipation per channel inhibit state, in conjunction with the integrated dynamic Driver clamps, facilitates the implementation of a high speed active 3-level voltage range: 1.5 V to +6.5 V termination. The output voltage capability is 1.5 V to +6.5 V Precision trimmed output resistance to accommodate a wide range of ATE and instrumentation Unterminated swing: 200 mV minimum to 8 V maximum applications. 725 ps minimum pulse width, VIH VIL = 2.0 V The ADATE318 can be used as a dual, single-ended drive/ Comparator receive channel or as a single differential drive/receive channel. Differential and single-ended window modes Each channel of the ADATE318 features a high speed window >1.2 GHz input equivalent bandwidth comparator as well as a programmable threshold differential Load comparator for differential ATE applications. A four quadrant 25 mA current range PPMU is also provided per channel. Per pin PPMU (PPMU) Force voltage/compliance range: 2.0 V to +6.5 V All dc levels for DCL and PPMU functions are generated by 24 5 current ranges: 40 mA, 1 mA, 100 A, 10 A, 2 A on-chip 16-bit DACs. To facilitate accurate levels programming, External sense input for system PMU the ADATE318 contains an integrated calibration function to Go/no-go comparators correct gain and offset errors for each functional block. Levels Correction coefficients can be stored on chip, and any values Fully integrated 16-bit DACs written to the DACs are automatically adjusted using the On-chip gain and offset calibration registers and appropriate correction factors. add/multiply engine The ADATE318 uses a serial programmable interface (SPI) bus Package to program all functional blocks, DACs, and on-chip calibration 84-lead 10 mm 10 mm LFCSP (0.4 mm pitch) constants. It also has an on-chip temperature sensor and APPLICATIONS over/undervoltage fault clamps for monitoring and reporting the device temperature and any output pin or PPMU voltage Automatic test equipment faults that may occur during operation. Semiconductor test systems Board test systems Instrumentation and characterization equipment Rev. B Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 20112017 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com ADATE318 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Control Register Details ................................................................ 55 Applications ....................................................................................... 1 Level Setting DACs ......................................................................... 63 General Description ......................................................................... 1 DAC Update Modes ................................................................... 63 Revision History ............................................................................... 2 DAC Transfer Functions ........................................................... 67 Functional Block Diagram .............................................................. 3 Gain and Offset Correction ...................................................... 68 Specifications ..................................................................................... 4 X Registers .................................................................................. 68 2 SPI Timing Details ..................................................................... 22 Sample Calculations of m and c ............................................... 68 Absolute Maximum Ratings .......................................................... 27 Power Supply, Grounding, and Decoupling Strategy ................ 70 Thermal Resistance .................................................................... 27 User Information and Truth Tables ............................................. 71 ESD Caution ................................................................................ 27 Alarm Functions ......................................................................... 72 Pin Configuration and Function Descriptions ........................... 28 PPMU External Capacitors ....................................................... 72 Typical Performance Characteristics ........................................... 31 Temperature Sensor ................................................................... 72 SPI Interconnect Details ................................................................ 49 Default Test Conditions ............................................................. 73 BUSY Detailed Functional Block Diagrams ........................................... 74 Use of the SPI Pin ................................................................ 50 Outline Dimensions ....................................................................... 80 Reset Sequence and the RST Pin .................................................. 51 Ordering Guide .......................................................................... 80 SPI Register Definitions and Memory Map ................................ 52 REVISION HISTORY 7/2017Rev. A to Rev. B 7/2011Rev. 0 to Rev. A Changes to Table 13 ........................................................................ 26 Updated Outline Dimensions ....................................................... 80 Changes to Figure 119 .................................................................... 57 Updated Outline Dimensions ....................................................... 80 4/2011Revision 0: Initial Version Changes to Ordering Guide .......................................................... 80 Rev. B Page 2 of 80