12-Bit CCD Signal Processor with V-Driver and Precision Timing Generator AD9920A FEATURES GENERAL DESCRIPTION Integrated 19-channel V-driver The AD9920A is a highly integrated charge-coupled device (CCD) 1.8 V AFETG core signal processor for digital still camera applications. It includes a 24 programmable vertical clock signals complete analog front end (AFE) with analog-to-digital conversion, Correlated double sampler (CDS) with 3 dB, 0 dB, combined with a full-function programmable timing generator +3 dB, and +6 dB gain and 19-channel vertical driver (V-driver). The timing generator 12-bit, 40.5 MHz analog-to-digital converter (ADC) is capable of supporting up to 24 vertical clock signals to control Black level clamp with variable level control advanced CCDs. The on-chip V-driver supports up to 19 channels Complete on-chip timing generator for use with six-field CCDs. A Precision Timing core allows adjust- Precision Timing core with ~400 ps resolution ment of high speed clocks with approximately 400 ps resolution On-chip 3 V horizontal and RG drivers at 40.5 MHz operation. The AD9920A also contains six GPOs General-purpose outputs (GPOs) for shutter and that can be used for shutter and system functions. system support The analog front end includes black level clamping, variable On-chip sync generator with external sync input gain CDS, and a 12-bit ADC. The timing generator provides all On-chip 1.8 V low dropout (LDO) regulator the necessary CCD clocks: RG, H-clocks, V-clocks, sensor gate 105-ball, 8 mm 8 mm CSP BGA package pulses, substrate clock, and substrate bias control. APPLICATIONS The AD9920A is specified over an operating temperature range Digital still cameras of 25C to +85C. FUNCTIONAL BLOCK DIAGRAM REFT REFB AD9920A 3dB, 0dB, +3dB, +6dB VREF 12 12-BIT CCDIN CDS VGA D0 TO D11 ADC 6dB TO 42dB CLAMP DCLK LDOIN LDO REG LDOOUT INTERNAL CLOCKS RG PRECISION HL HORIZONTAL TIMING DRIVERS SL GENERATOR 8 INTERNAL H1 TO H8 SCK REGISTERS XV1 TO XV24 SDATA 19 V1A TO V6 (3-LEVEL) VERTICAL V7 TO V16 (2-LEVEL) 24 VERTICAL TIMING SYNC GPO5 DRIVER CONTROL GENERATOR GPO6 SUBCK 6 XSUBCK XSUBCNT GPO1 TO GPO4, HD VD CLI CLO SYNC/RST GPO7, GPO8 Figure 1. Rev. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. 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Trademarks and registered trademarks are the property of their respective owners. 06878-001AD9920A TABLE OF CONTENTS Features .............................................................................................. 1 V-Driver Slew Rate Control ...................................................... 60 Applications ....................................................................................... 1 Shutter Timing Control ............................................................. 60 General Description ......................................................................... 1 Substrate Clock Operation (SUBCK) ...................................... 60 Functional Block Diagram .............................................................. 1 Field Counters ............................................................................. 63 Revision History ............................................................................... 3 General-Purpose Outputs (GPOs) .......................................... 64 Specif icat ions ..................................................................................... 4 GP Lookup Table (LUT) ............................................................ 68 Digital Specifications ................................................................... 5 Complete Exposure/Readout Operation Using Primary Counter and GPO Signals ......................................................... 69 Analog Specifications ................................................................... 5 SG Control Using GPO ............................................................. 71 Timing Specifications .................................................................. 7 Manual Shutter Operation Using Enhanced SYNC Modes .. 73 Vertical Driver Specifications ..................................................... 8 Analog Front End Description and Operation ...................... 77 Absolute Maximum Ratings .......................................................... 10 Applications Information .............................................................. 79 Thermal Resistance .................................................................... 10 Power-Up Sequence for Master Mode ..................................... 79 ESD Caution ................................................................................ 10 Power-Up Sequence for Slave Mode ........................................ 81 Pin Configuration and Function Descriptions ........................... 11 Power-Down Sequence for Master and Slave Modes ............ 83 Typical Performance Characteristics ........................................... 14 Additional Restrictions in Slave Mode .................................... 84 Equivalent Circuits ......................................................................... 15 Vertical Toggle Position Placement Near Counter Reset ...... 85 Terminology .................................................................................... 16 Standby Mode Operation .......................................................... 86 Theory of Operation ...................................................................... 17 CLI Frequency Change .............................................................. 86 H-Counter Behavior in Slave Mode ......................................... 17 Circuit Layout Information ........................................................... 88 High Speed Precision Timing Core ........................................... 18 Typical 3 V System ..................................................................... 88 Digital Data Outputs .................................................................. 22 External Crystal Application .................................................... 88 Horizontal Clamping and Blanking ......................................... 23 Circuit Configurations .............................................................. 89 Horizontal Timing Sequence Example .................................... 30 Serial Interface ................................................................................ 93 Vertical Timing Generation ...................................................... 32 Serial Interface Timing .............................................................. 93 Vertical Sequences (VSEQ) ....................................................... 34 Layout of Internal Registers ...................................................... 94 Vertical Timing Example ........................................................... 51 Updating New Register Values ................................................. 95 Internal Vertical Driver Connections (18-Channel Mode) .. 53 Complete Register Listing ............................................................. 96 Internal Vertical Driver Connections (19-Channel Mode) .. 54 Outline Dimensions ..................................................................... 112 Output Polarity of Vertical Transfer Clocks and Substrate Clock ............................................................................................ 55 Ordering Guide ........................................................................ 112 Rev. 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