a Bridge Transducer ADC AD7730/AD7730L The modulator output is processed by a low pass programmable KEY FEATURES digital filter, allowing adjustment of filter cutoff, output rate and Resolution of 230,000 Counts (Peak-to-Peak) settling time. Offset Drift: 5 nV/ C Gain Drift: 2 ppm/ C The part features two buffered differential programmable gain Line Frequency Rejection: >150 dB analog inputs as well as a differential reference input. The part Buffered Differential Inputs operates from a single +5 V supply. It accepts four unipolar Programmable Filter Cutoffs analog input ranges: 0 mV to +10 mV, +20 mV, +40 mV and Specified for Drift Over Time +80 mV and four bipolar ranges: 10 mV, 20 mV, 40 mV Operates with Reference Voltages of 1 V to 5 V and 80 mV. The peak-to-peak resolution achievable directly from the part is 1 in 230,000 counts. An on-chip 6-bit DAC ADDITIONAL FEATURES allows the removal of TARE voltages. Clock signals for synchro- Two-Channel Programmable Gain Front End nizing ac excitation of the bridge are also provided. On-Chip DAC for Offset/TARE Removal The serial interface on the part can be configured for three-wire FASTStep Mode operation and is compatible with microcontrollers and digital AC or DC Excitation signal processors. The AD7730 contains self-calibration and Single Supply Operation system calibration options, and features an offset drift of less APPLICATIONS than 5 nV/C and a gain drift of less than 2 ppm/C. Weigh Scales The AD7730 is available in a 24-pin plastic DIP, a 24-lead Pressure Measurement SOIC and 24-lead TSSOP package. The AD7730L is available in a 24-lead SOIC and 24-lead TSSOP package. GENERAL DESCRIPTION The AD7730 is a complete analog front end for weigh-scale and NOTE pressure measurement applications. The device accepts low- The description of the functions and operation given in this data level signals directly from a transducer and outputs a serial sheet apply to both the AD7730 and AD7730L. Specifications digital word. The input signal is applied to a proprietary pro- and performance parameters differ for the parts. Specifications grammable gain front end based around an analog modulator. for the AD7730L are outlined in Appendix A. FUNCTIONAL BLOCK DIAGRAM REF IN() AV DV REF IN(+) DD DD AD7730 REFERENCE DETECT VBIAS AV DD STANDBY AIN1(+) SIGMA-DELTA A/D CONVERTER BUFFER 100nA AIN1() SIGMA- PROGRAMMABLE SYNC DELTA DIGITAL + MUX PGA MODULATOR FILTER +/ AIN2(+)/D1 100nA MCLK IN CLOCK 6-BIT AIN2()/D0 GENERATION AGND SERIAL INTERFACE MCLK OUT DAC AND CONTROL LOGIC REGISTER BANK SCLK CS CALIBRATION DIN MICROCONTROLLER ACX AC DOUT EXCITATION ACX CLOCK AGND DGND POL RDY RESET FASTStep is a trademark of Analog Devices, Inc. REV. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. use, nor for any infringements of patents or other rights of third parties Tel: 781/329-4700 World Wide Web Site: (AV = +5 V, DV = +3 V or +5 V REF IN(+) = AV REF IN() = AGND = DGND = DD DD DD AD7730SPECIFICATIONS 0 V f = 4.9152 MHz. All specifications T to T unless otherwise noted.) CLK IN MIN MAX 1 Parameter B Version Units Conditions/Comments STATIC PERFORMANCE (CHP = 1) 2 No Missing Codes 24 Bits min 2 Output Noise and Update Rates See Tables I & II Integral Nonlinearity 18 ppm of FSR max 2 Offset Error See Note 3 Offset Error and Offset Drift Refer to Both 2 Offset Drift vs. Temperature 5 nV/C typ Unipolar Offset and Bipolar Zero Errors 4 Offset Drift vs. Time 25 nV/1000 Hours typ 2, 5 Positive Full-Scale Error See Note 3 2, 6, 7 Positive Full-Scale Drift vs Temp 2 ppm of FS/C max 4 Positive Full-Scale Drift vs Time 10 ppm of FS/1000 Hours typ 2, 8 Gain Error See Note 3 2, 6, 9 Gain Drift vs. Temperature 2 ppm/C max 4 Gain Drift vs. Time 10 ppm/1000 Hours typ 2 Bipolar Negative Full-Scale Error See Note 3 2, 6 Negative Full-Scale Drift vs. Temp 2 ppm of FS/C max Power Supply Rejection 120 dB typ Measured with Zero Differential Voltage Common-Mode Rejection (CMR) 120 dB min At DC. Measured with Zero Differential Voltage 2 Analog Input DC Bias Current 50 nA max 2 Analog Input DC Bias Current Drift 100 pA/C typ 2 Analog Input DC Offset Current 10 nA max 2 Analog Input DC Offset Current Drift 50 pA/C typ 2 STATIC PERFORMANCE (CHP = 0) 10 No Missing Codes 24 Bits min SKIP = 0 Output Noise and Update Rates See Tables III & IV Integral Nonlinearity 18 ppm of FSR max Offset Error See Note 3 Offset Error and Offset Drift Refer to Both 6 Offset Drift vs. Temperature 0.5 V/C typ Unipolar Offset and Bipolar Zero Errors 4 Offset Drift vs. Time 2.5 V/1000 Hours typ 5 Positive Full-Scale Error See Note 3 6, 7 Positive Full-Scale Drift vs. Temp 0.6 V/C typ 4 Positive Full-Scale Drift vs. Time 3 V/1000 Hours typ 8 Gain Error See Note 3 6, 9 Gain Drift vs. Temperature 2 ppm/C typ 4 Gain Drift vs. Time 10 ppm/1000 Hours typ Bipolar Negative Full-Scale Error See Note 3 Negative Full-Scale Drift vs. Temp 0.6 V/C typ Power Supply Rejection 90 dB typ Measured with Zero Differential Voltage Common-Mode Rejection (CMR) on AIN 100 dB typ At DC. Measured with Zero Differential Voltage CMR on REF IN 120 dB typ At DC. Measured with Zero Differential Voltage Analog Input DC Bias Current 60 nA max Analog Input DC Bias Current Drift 150 pA/C typ Analog Input DC Offset Current 30 nA max Analog Input DC Offset Current Drift 100 pA/C typ ANALOG INPUTS/REFERENCE INPUTS 2 Normal-Mode 50 Hz Rejection 88 dB min From 49 Hz to 51 Hz 2 88 dB min From 59 Hz to 61 Hz Normal-Mode 60 Hz Rejection 2 Common-Mode 50 Hz Rejection 120 dB min From 49 Hz to 51 Hz 2 Common-Mode 60 Hz Rejection 120 dB min From 59 Hz to 61 Hz Analog Inputs 11 Differential Input Voltage Ranges Assuming 2.5 V or 5 V Reference with HIREF Bit Set Appropriately 0 to +10 or 10 mV nom Gain = 250 0 to +20 or 20 mV nom Gain = 125 0 to +40 or 40 mV nom Gain = 62.5 0 to +80 or 80 mV nom Gain = 31.25 12 Absolute/Common-Mode Voltage AGND + 1.2 V V min AV 0.95 V V max DD Reference Input REF IN(+) REF IN() Voltage +2.5 V nom HIREF Bit of Mode Register = 0 REF IN(+) REF IN() Voltage +5 V nom HIREF Bit of Mode Register = 1 13 AGND 30 mV V min Absolute/Common-Mode Voltage AV + 30 mV V max DD NO REF Trigger Voltage 0.3 V min NO REF Bit Active If V Below This Voltage REF 0.65 V max NO REF Bit Inactive If V Above This Voltage REF REV. B 2