Dual Channel, Gain-Ranging a ADC with RSSI AD6600 FEATURES two input channels, each with 1 GHz input amplifiers and Dual IF Inputs, 70 MHz250 MHz 30 dB of automatic gain-ranging circuitry. Both channels are Diversity or Two Independent IF Signals sampled with a 450 MHz track-and-hold followed by an 11-bit, Separate Attenuation Paths 20 MSPS analog-to-digital converter. Digital RSSI outputs, an Oversample RF Channels A/B channel indicator, a 2 Clock output, references, and con- 20 MSPS on a Single Carrier trol circuitry are all on-chip. Digital output signals are twos 10 MSPS/Channel in Diversity Mode complement, CMOS-compatible and interface directly to Total Signal Range 90+ dB 3.3 V or 5 V digital processing chips. 30 dB from Automatic Gain-Ranging (AGC) The primary use for the dual analog input structure is sampling 60 dB from A/D Converter both antennas in a two-antenna diversity receiver. However, Range >100 dB After Processing Gain Channels A and B may also be used to sample two independent Digital Outputs IF signals. Diversity, or dual-channel mode, is limited to 10 MSPS 11-Bit ADC Word per channel. In single-channel mode, the full clock rate of 3-Bit RSSI Word 20 MSPS may be applied to a single carrier. 2 Clock, A/B Indicator The AD6600 may be used as a stand-alone sampling chip, or it Single 5 V Power Supply may be combined with the AD6620 Digital Receive Signal Pro- Output DVCC 3.3 V or 5 V cessor. The AD6620 provides 10 dB25 dB of additional pro- 775 mW Power Dissipation cessing gain before passing data to a fixed- or floating-point DSP. APPLICATIONS Driving the AD6600 is simplified by using the AD6630 differen- Communications Receivers tial IF amplifier. The AD6630 is easily matched to inexpensive PCS/Cellular Base Stations SAW filters from 70 MHz to 250 MHz. GSM, CDMA, TDMA Designed specifically for cellular/PCS receivers, the AD6600 Wireless Local Loop, Fixed Access supports GSM, IS-136, CDMA and Wireless LANs, as well as proprietary air interfaces used in WLL/fixed-access systems. PRODUCT DESCRIPTION Units are available in plastic, surface-mount packages (44-lead The AD6600 mixed-signal receiver chip directly samples signals LQFP) and specified over the industrial temperature range at analog input frequencies up to 250 MHz. The device includes (40C to +85C). FUNCTIONAL BLOCK DIAGRAM NOISE FILTER FLT FLT RESONANT 0dB, 12dB, 24dB 630 PORT AIN ATTEN AIN AB OUT ENCODE +12, +18dB GAIN TWO S COMPLEMENT A/D 3 D10D0 GAIN DETECT SET CONVERTER PEAK RSSI 11 RSSI 3 GAIN RSSI 2:0 RSSI SELECT GAIN ENCODE BIN ATTEN BIN TIMING CLK2 AD6600 0dB, 12dB, 24dB A SEL B SEL AVCC GND ENC ENC DVCC REV. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or Tel: 781/329-4700 World Wide Web Site: AD6600SPECIFICATIONS DC SPECIFICATIONS (AVCC = 5 V, DVCC = 3.3 V T = 40 C, T = +85 C unless otherwise noted.) MIN MAX Test AD6600AST Parameter Temp Level Min Typ Max Unit ANALOG INPUTS (AIN, AIN/BIN, BIN) 1 Differential Analog Input Voltage Range Full V 2.0 V p-p 2 Differential Analog Input Resistance Full IV 160 200 240 Differential Analog Input Capacitance 25C V 1.5 pF PEAK DETECTOR (Internal), RSSI Resolution 3 Bits RSSI Gain Step Full V 6 dB 3 RSSI Hysteresis Full V 6 dB RESONANT PORT (FLT, FLT) Differential Port Resistance Full V 630 Differential Port Capacitance Full V 1.75 pF A/D CONVERTER Resolution Full IV 11 Bits ENCODE INPUTS (ENC, ENC) 4 Differential Input Voltage (AC-Coupled) Full IV 0.4 V p-p Differential Input Resistance 25CV 11 k Differential Input Capacitance 25C V 2.5 pF 5 A/B MODE INPUTS (A SEL, B SEL) Input High Voltage Range Full IV 4.75 5.25 V Input Low Voltage Range Full IV 0.0 0.5 V POWER SUPPLY Supply Voltages AVCC Full II 4.75 5.0 5.25 V DVCC Full IV 3.0 3.3 5.25 V Supply Current I (AVCC = 5.0 V) Full II 145 182 mA AVCC I (DVCC = 3.3 V) Full II 15 20 mA DVCC 6 POWER CONSUMPTION Full II 775 976 mW NOTES 1 Analog Input Range is a function of input frequency. See ac specifications for 70 MHz250 MHz inputs. 2 Analog Input Impedance is a function of input frequency. See ac specifications for 70 MHz450 MHz inputs. 3 Six dB of digital hysteresis is used to eliminate level uncertainty at the RSSI threshold points due to noise and amplitude variations. 4 Encode inputs should be ac-coupled and driven differentially. See Encoding the AD6600 for details. 5 A SEL and B SEL should be tied directly to ground or AVCC. 6 Maximum power consumption is computed as maximum current at nominal supplies. Specifications subject to change without notice. DIGITAL SPECIFICATIONS (AVCC = 5 V, DVCC = 3.3 V T = 40 C, T = +85 C unless otherwise noted.) MIN MAX Test AD6600AST Parameter Temp Level Min Typ Max Unit 1 LOGIC OUTPUTS (D10D0, AB OUT, RSSI20) Logic Compatibility CMOS Logic 1 Voltage (DVCC = 3.3 V) Full II 2.8 DVCC 0.2 V Logic 0 Voltage (DVCC = 3.3 V) Full II 0.2 0.5 V Logic 1 Voltage (DVCC = 5.0 V) Full IV 4.0 DVCC 0.35 V Logic 0 Voltage (DVCC = 5.0 V) Full IV 0.35 0.5 V Output Coding (D10D0) Twos Complement 1, 2 CLK2 OUTPUT Logic 1 Voltage (DVCC = 3.3 V) Full II 2.8 DVCC 0.2 V Logic 0 Voltage (DVCC = 3.3 V) Full II 0.2 0.5 V Logic 1 Voltage (DVCC = 5.0 V) Full IV 4.0 DVCC 0.3 V Logic 0 Voltage (DVCC = 5.0 V) Full IV 0.35 0.5 V NOTES 1 Digital output load is one LCX gate. 2 CLK2 output voltage levels, high and low, tested at switching rate of 10 MHz. Specifications subject to change without notice. 2 REV. 0