March 2004 AS7C513B 5V 32K16 CMOS SRAM Features Industrial and commercial temperature Easy memory expansion with CE, OE inputs Organization: 32,768 words 16 bits TTL-compatible, three-state I/O Center power and ground pins 44-pin JEDEC standard package High speed 400 mil SOJ 10/12/15/20 ns address access time 400 mil TSOP 2 5, 6, 7, 8 ns output enable access time ESD protection > 2000 volts Low power consumption: ACTIVE Latch-up current > 200 mA 605mW / max 10 ns Low power consumption: STANDBY 55 mW / max CMOS I/O 6T 0.18u CMOS Technology Logic block diagram Pin arrangement A0 44-Pin SOJ, TSOP 2 (400 mil) V CC A1 A2 32K 16 GND NC 1 44 A4 A3 A3 2 43 A5 Array A4 A2 3 42 A6 A1 4 41 OE A5 A0 5 40 UB A6 CE 6 39 LB A7 I/O0 7 38 I/O15 I/O1 8 37 I/O14 I/O2 9 36 I/O13 I/O0I/O7 I/O Control circuit buffer I/O3 10 35 I/O12 I/O8I/O15 V 11 34 GND CC GND 12 33 V CC Column decoder I/O4 13 32 I/O11 WE I/O5 14 31 I/O10 I/O6 15 30 I/O9 I/O7 16 29 I/O8 WE 17 28 NC A14 18 27 A7 UB A13 19 26 A8 OE A12 20 25 A9 A11 21 24 A10 LB NC 22 23 NC CE Selection guide -10 -12 -15 -20 Unit Maximum address access time 10 12 15 20 ns Maximum output enable access time 56 7 8 ns Maximum operating current 110 100 90 80 mA Maximum CMOS standby current 10 10 10 10 mA 3/26/04, v.1.3 Alliance Semiconductor P. 1 of 9 Copyright Alliance Semiconductor. All rights reserved. Row decoder A8 A9 A10 A11 A12 A13 A14 AS7C513BAS7C513B Functional description The AS7C513B is a high performance CMOS 524,288-bit Static Random Access Memory (SRAM) device organized as 32,768 words 16 bits. They are designed for memory applications where fast data access, low power, and simple interfacing are desired. Equal address access and cycle times (t , t , t ) of 10/12/15/20 ns with output enable access times (t ) of 5, 6, 7, 8 ns are ideal for AA RC WC OE high performance applications. The chip enable input CE permits easy memory expansion with multiple-bank memory systems. When CE is high, the device enters standby mode. If inputs are still toggling, the device consumes I power. If the bus is static, then the full SB standby power is reached (I ). The AS7C513B is guaranteed not to exceed 55mW power consumption under nominal full standby SB1 conditions. A write cycle is accomplished by asserting write enable (WE), (UB) and/or (LB), and chip enable (CE). Data on the input pins I/O0 - I/O7, and/or I/O8 I/O15, is written on the rising edge of WE (write cycle 1) or CE (write cycle 2). To avoid bus contention, external devices should drive I/O pins only after outputs have been disabled with output enable (OE) or write enable (WE). A read cycle is accomplished by asserting output enable (OE), (UB) and (LB), and chip enable (CE), with write enable (WE) high. The chips drive I/O pins with the data word referenced by the input address. When either chip enable or output enable is inactive, or write enable is ) and (LB), output drivers stay in high-impedance mode. active, or (UB The devices provide multiple center power and ground pins, and separate byte enable controls, allowing individual bytes to be written and read. LB controls the lower bits, I/O0 I/O7, and UB controls the higher bits, I/O8 I/O15. All chip inputs and outputs are TTL-compatible. The AS7C513B is packaged in common industry standard packages. Absolute maximum ratings Parameter Symbol Min Max Unit Voltage on V relative to GND V 0.50 +7.0 V CC t1 Voltage on any pin relative to GND V 0.50 V +0.50 V t2 CC Power dissipation P 1.0 W D o Storage temperature (plastic) T 65 +150 C stg o Ambient temperature with V applied T 55 +125 C CC bias DC current into outputs (low) I 20 mA OUT NOTE: Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and func- tional operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Truth table CE WE OE LB UB I/O0I/O7 I/O8I/O15 Mode H X X X X High Z High Z Standby (I , I ) SB SBI LHL L H D High Z Read I/O0I/O7 (I ) OUT CC LHLHL High Z D Read I/O8I/O15 (I ) OUT CC L H LLL D D Read I/O0I/O15 (I ) OUT OUT CC LL X L L D D Write I/O0I/O15 (I ) IN IN CC LL X L H D High Z Write I/O0I/O7 (I ) IN CC LL X H L High Z D Write I/O8I/O15 (I ) IN CC L H H X X High Z High Z Output disable (I ) CC L X X H H Key: X = Dont care L = Low H = High 3/26/04, v.1.3 Alliance Semiconductor P. 2 of 9