AS4C8M32MD2A-25BCN Revision History 256M Mobile DDR2 AS4C8M32MD2A-25BCN 134ball FBGA PACKAGE Revision Details Date Rev 1.0 Preliminary datasheet Jun. 2018 Alliance Memory Inc. 511 Taylor Way, San Carlos, CA 94070 TEL: (650) 610-6800 FAX: (650) 620-9211 Alliance Memory Inc. reserves the right to change products or specification without notice Confidential - 1 of 75 - Rev.1.0 Jun. 2018AS4C8M32MD2A-25BCN 8M x 32 Mobile LPDDR2 Synchronous DRAM (SDRAM) Advance (Rev. 1. 0, Jun. /2018) Features Overview Fast clock rate: 400 MHz The AS4C8M32MD2A LPDDR2 SDRAM is a high-speed CMOS, dynamic random-access Differential Clock inputs CK/CK memory containing 268,435,456 bits. It is internally JEDEC standard Compliant configured as a 4 banks of 2,097,152 words by 32 Four-bit prefetch DDR architecture bits memory device. The devices use double data Four internal banks, 2M x 32-bit for each bank rate architecture on the command/address (CA) bus Double data rate architecture for command, address to reduce the number of input pins in the system. The and data Bus 10-bit CA bus contains command, address, and Bidirectional/differential data strobe per byte of data Bank/Row Buffer information. Each command uses DQS/DQS one clock cycle, during which command information Programmable Mode Registers is transferred on both the positive and negative edge of the clock. LPDDR2 also use double data - READ and WRITE latencies (RL/WL) rate architecture on the DQ pins to achieve high - Burst length: 4, 8, or 16 speed operation. The double data rate - PASR (Partial Array Self Refresh) architecture is essentially a 4n prefetch Auto TCSR (Temperature Compensated Self Refresh) architecture with an interface designed to transfer Auto Refresh and Self Refresh two data bits per DQ every clock cycle at the I/O Deep power-down pins. A single read or write access for the 4096 refresh cycles / 32ms LPDDR2 effectively consists of a single 4n-bit wide, Power supplies: one clock cycle data transfer at the internal SDRAM/ NVM core and four corresponding n-bit wide, one- - V = 1.8V (1.7V~1.95V) DD1 half-clock-cycle data transfers at the I/O pins. Read - V = 1.2V (1.14V~1.3V) DD2 and write accesses to the LPDDR2 are burst - V /V = 1.2V (1.14V~1.3V) DDCA DDQ oriented accesses start at a selected location Interface: HSUL 12 and continue for a programmed number of Operating Temperature: TC = -25 ~ 85C locations in a programmed sequence. Package: 134-ball 10 x 11.5 x 1.0mm (max) FBGA - Pb Free and Halogen Free Table 1. Ordering Information Org. Product Part No. Temperature Max Clock (MHz) Package AS4C8M32MD2A-25BCN 8M x 32 -25C to 85C 134-ball FBGA 400 Table 2. Speed Grade Information t (ns) RL WL t (ns) Speed Grade Clock Frequency RCD RP 400 MHz DDR2L-800 6 3 18 18 Confidential - 2 of 75 - Rev.1.0 Jun. 2018