74LV4066D,112

74LV4066 Quad bilateral switches Rev. 4 9 December 2015 Product data sheet 1. General description The 74LV4066 is a low-voltage Si-gate CMOS device that is pin and function compatible with the 74HC4066 and 74HCT4066. The 74LV4066 has four independent switches. Each switch has two input/output pins (nY, nZ) and an active HIGH enable input pin (nE). When nE is LOW the corresponding analog switch is turned off. The 74LV4066 has a ON-resistance which is reduced in comparison with the 74HCT4066. 2. Features and benefits Optimized for low-voltage applications: 1.0 V to 3.6 V Typical V (output ground bounce): < 0.8 V at V = 3.3 V and T = 25 C OLP CC amb Accepts TTL input levels between V = 2.7 V and V = 3.6 V CC CC Very low ON-resistance: 60 (typical) at V =2.0V CC 35 (typical) at V =3.0V CC 25 (typical) at V =4.5V CC ESD protection: HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-A exceeds 200 V Specified from 40 Cto+80 C and from 40 Cto+125 C 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74LV4066D 40 C to +125 C SO14 plastic small outline package 14 leads body width 3.9 mm SOT108-1 74LV4066DB 40 C to +125 C SSOP14 plastic shrink small outline package 14 leads SOT337-1 body width 5.3 mm 74LV4066PW 40 C to +125 C TSSOP14 plastic thin shrink small outline package 14 leads SOT402-1 body width 4.4 mm74LV4066 Nexperia Quad bilateral switches 4. Functional diagram D E D DG GDD Fig 1. Logic symbol Fig 2. IEC logic diagram Q< Q( 9 9 Q = Fig 3. Logic diagram (one switch) 74LV4066 All information provided in this document is subject to legal disclaimers. Nexperia B.V. 2017. All rights reserved Product data sheet Rev. 4 9 December 2015 2 of 22 DDG *1 && && ( = < ( = < ( = < ( = <