1Gb: x16, x32 Mobile LPDDR SDRAM
Features
Mobile Low-Power DDR SDRAM
MT46H64M16LF 16 Meg x 16 x 4 banks
MT46H32M32LF 8 Meg x 32 x 4 banks
Options Marking
Features
V /V
DD DDQ
V /V = 1.701.95V
DD DDQ
1.8V/1.8V H
Bidirectional data strobe per byte of data (DQS)
Configuration
Internal, pipelined double data rate (DDR) 64 Meg x 16 (16 Meg x 16 x 4 64M16
architecture; two data accesses per clock cycle banks)
32 Meg x 32 (8 Meg x 32 x 4 banks) 32M32
Differential clock inputs (CK and CK#)
Addressing
Commands entered on each positive CK edge
JEDEC-standard LF
DQS edge-aligned with data for READs; center-
Plasticgree package
aligned with data for WRITEs
1
60-ball VFBGA (8mm x 9mm) BF
4 internal banks for concurrent operation
2
90-ball VFBGA (8mm x 13mm) B5
Data masks (DM) for masking write data; one mask
PoP (plasticgree package)
2
per byte
168-ball WFBGA (12mm x 12mm) MA
Programmable burst lengths (BL): 2, 4, 8, or 16 Timing cycle time
5ns @ CL = 3 (200 MHz) -5
Concurrent auto precharge option is supported
5.4ns @ CL = 3 (185 MHz) -54
Auto refresh and self refresh modes
6ns @ CL = 3 (166 MHz) -6
1.8V LVCMOS-compatible inputs
7.5ns @ CL = 3 (133 MHz) -75
Temperature-compensated self refresh (TCSR)
Power
Partial-array self refresh (PASR)
Standard I /I None
DD2 DD6
Deep power-down (DPD) Operating temperature range
Commercial (0 to +70C) None
Status read register (SRR)
Industrial (40C to +85C) IT
Selectable output drive strength (DS)
3
Automotive (40C to +105C) AT
Clock stop capability
Design revision :B
64ms refresh, 32ms for automotive temperature
1. Only available for x16 configuration.
Notes:
2. Only available for x32 configuration.
Table 1: Key Timing Parameters (CL = 3)
3. Contact factory for availability.
Speed Grade Clock Rate Access Time
-5 200 MHz 5.0ns
-54 185 MHz 5.0ns
-6 166 MHz 5.0ns
-75 133 MHz 6.0ns
PDF: 09005aef83d9bee4 Micron Technology, Inc. reserves the right to change products or specifications without notice.
1
1gb_ddr_mobile_sdram_t68m.pdf - Rev. K 10/2018 EN 2009 Micron Technology, Inc. All rights reserved.
Products and specifications discussed herein are subject to change by Micron without notice.1Gb: x16, x32 Mobile LPDDR SDRAM
Features
Table 2: Configuration Addressing
Architecture 64 Meg x 16 32 Meg x 32
Configuration 16 Meg x 16 x 4 banks 8 Meg x 32 x 4 banks
Refresh count 8K 8K
Row addressing 16K A[13:0] 8K A[12:0]
Column addressing 1K A[9:0] 1K A[9:0]
Figure 1: 1Gb Mobile LPDDR Part Numbering
MT 46 H 64M16 LF BF -6 IT :B
Micron Technology Design Revision
:B = Second generation
Product Family
46 = Mobile LPDDR Operating Temperature
Blank = Commercial (0C to +70C)
Operating Voltage IT = Industrial (40C to +85C)
H = 1.8/1.8V AT = Automotive (40C to +105C)
Configuration Power
64 Meg x 16 Blank = Standard I /I
DD2 DD6
32 Meg x 32
Cycle Time (CL = 3)
t
Addressing -5 = 5ns CK
t
LF = JEDEC-standard -54 = 5.4ns CK
t
-6 = 6ns CK
t
-75 = 7.5ns CK
Package Codes
BF = 60-ball (8mm x 9mm) VFBGA, green
B5 = 90-ball (8mm x 13mm) VFBGA, green
MA = 168-ball (12mm x 12mm) WFBGA, green
FBGA Part Marking Decoder
Due to space limitations, FBGA-packaged components have an abbreviated part marking that is different from the
part number. Microns FBGA part marking decoder is available at www.micron.com/decoder.
PDF: 09005aef83d9bee4 Micron Technology, Inc. reserves the right to change products or specifications without notice.
2
1gb_ddr_mobile_sdram_t68m.pdf - Rev. K 10/2018 EN 2009 Micron Technology, Inc. All rights reserved.