ADVANCED LINEAR DEVICES, INC. ALD1103 DUAL N-CHANNEL AND DUAL P-CHANNEL MATCHED MOSFET PAIR GENERAL DESCRIPTION APPLICATIONS The ALD1103 is a monolithic dual N-channel and dual P-channel Precision current mirrors matched transistor pair intended for a broad range of analog applications. Complementary push-pull linear drives These enhancement-mode transistors are manufactured with Advanced Analog switches Linear Devices enhanced ACMOS silicon gate CMOS process. It Choppers consists of an ALD1101 N-channel MOSFET pair and an ALD1102 P- Differential amplifier input stage channel MOSFET pair in one package. Voltage comparator Data converters The ALD1103 offers high input impedance and negative current tempera- Sample and Hold ture coefficient. The transistor pair is matched for minimum offset voltage Analog inverter and differential thermal response, and it is designed for precision signal Precision matched current sources switching and amplifying applications in +2V to +10V systems where low input bias current, low input capacitance and fast switching speed are PIN CONFIGURATION desired. Since these are MOSFET devices, they feature very large (almost infinite) current gain in a low frequency, or near DC, operating DN1 1 14 DN2 environment. When used in pairs, a dual CMOS analog switch can be constructed. In addition, the ALD1103 is intended as a building block for GN1 2 13 GN2 differential amplifier input stages, transmission gates, and multiplexer applications. SN1 3 12 SN2 The ALD1103 is suitable for use in precision applications which require - V 4 + 11 V very high current gain, beta, such as current mirrors and current sources. The high input impedance and the high DC current gain of the Field Effect 5 DP1 10 DP2 Transistors result in extremely low current loss through the control gate. The DC current gain is limited by the gate input leakage current, which is GP2 GP1 6 9 specified at 50pA at room temperature. For example, DC beta of the device at a drain current of 5mA at 25C is = 5mA/50pA = 100,000,000. SP1 7 8 SP2 TOP VIEW SBL, PBL PACKAGES FEATURES Thermal tracking between N-channel and P-channel pairs Low threshold voltage of 0.7V for both N-channel & BLOCK DIAGRAM P-channel MOSFETS N GATE 1 (2) Low input capacitance Low Vos -- 10mV 13 High input impedance -- 10 typical N SOURCE 1 (3) N DRAIN 1 (1) Low input and output leakage currents Negative current (I ) temperature coefficient DS SUBSTRATE (4) Enhancement mode (normally off) 9 N DRAIN 2 (14) N SOURCE 2 (12) DC current gain 10 Matched N-channel and matched P-channel in one package RoHS compliant N GATE 2 (13) ORDERING INFORMATION (L suffix denotes lead-free (RoHS)) P GATE 1 (6) Operating Temperature Range* 0C to +70C0C to +70C P DRAIN 1 (5) P SOURCE 1 (7) 14-Pin 14-Pin SUBSTRATE (11) SOIC Plastic Dip Package Package P DRAIN 2 (10) P SOURCE 2 (8) ALD1103SBL ALD1103PBL * Contact factory for high temperature versions. P GATE 2 (9) 2021 Advanced Linear Devices, Inc., Vers. 2.2 www.aldinc.com 1 of 8ABSOLUTE MAXIMUM RATINGS Drain-source voltage, V 10V DS Gate-source voltage, V 10V GS Power dissipation 500mW Operating temperature range SBL, PBL packages 0C to +70C Storage temperature range -65C to +150C Lead temperature, 10 seconds +260C CAUTION: ESD Sensitive Device. Use static control procedures in ESD controlled environment. OPERATING ELECTRICAL CHARACTERISTICS T = 25C unless otherwise specified A N - Channel Test P - Channel Test Parameter Symbol Min Typ Max Unit Conditions Min Typ Max Unit Conditions Gate Threshold V 0.4 0.7 1.0 V I = 10A V = V -0.4 -0.7 -1.2 V I = -10A V = V T DS GS DS DS GS DS Voltage Offset Voltage V 10 mV I = 100A V = V 10 mV I = -100A V = V OS DS GS DS DS GS DS V - V GS1 GS2 Gate Threshold Temperature TC -1.2 mV/C -1.3 mV/C VT Drift On Drain I 25 40 mA V = V = 5V -8 -16 mA V = V = -5V DS(ON) GS DS GS DS Current Trans-. G 5 10 mmho V = 5V I = 10mA 2 4 mmho V = -5V I = -10mA fs DS DS DS DS conductance Mismatch G 0.5 % 0.5 % fs Output G 200 mho V = 5V I = 10mA 500 mho V = -5V I = -10mA OS DS DS DS DS Conductance Drain Source R 50 75 V = 0.1V V = 5V 180 270 V = -0.1V V = -5V DS(ON) DS GS DS GS ON Resistance Drain Source ON Resistance R 0.5 % V = 0.1V V = 5V 0.5 % V = -0.1V V = -5V DS(ON) DS GS DS GS Mismatch Drain Source Breakdown BV 10 V I = 10A V = 0V -10 V I = -10A V = 0V DSS DS GS DS GS Voltage Off Drain I 0.1 4 nA V = 10V I = 0V 0.1 4 nA V = -10V V = 0V DS(OFF) DS GS DS GS Current 4 AT = 125C4 AT = 125C A A Gate Leakage I 1 100 pA V = 0V V = 10V 1 100 pA V = 0V V = -10V GSS DS GS DS GS Current 10 nA T = 125C10nAT = 125C A A Input C 610 pF 6 10pF ISS Capacitance ALD1103 Advanced Linear Devices 2 of 8