ADVANCED LINEAR ALD1101A/ALD1101B DEVICES, INC. ALD1101 DUAL N-CHANNEL MATCHED MOSFET PAIR GENERAL DESCRIPTION APPLICATIONS The ALD1101 is a monolithic dual N-channel matched transistor pair Precision current mirrors intended for a broad range of analog applications. These enhancement- Precision current sources mode transistors are manufactured with Advanced Linear Devices Analog switches enhanced ACMOS silicon gate CMOS process. Choppers Differential amplifier input stage The ALD1101 offers high input impedance and negative current tempera- Voltage comparator ture coefficient. The transistor pair is matched for minimum offset voltage Data converters and differential thermal response, and it is designed for switching and Sample and Hold amplifying applications in +2V to +10V systems where low input bias Analog inverter current, low input capacitance and fast switching speed are desired. Since these are MOSFET devices, they feature very large (almost infinite) current gain in a low frequency, or near DC, operating environment. When used with an ALD1102, a dual CMOS analog switch can be constructed. In addition, the ALD1101 is intended as a building block for PIN CONFIGURATION differential amplifier input stages, transmission gates, and multiplexer applications. 1 8 SUBSTRATE SOURCE The ALD1101 is suitable for use in precision applications which require 1 very high current gain, beta, such as current mirrors and current sources. SOURCE GATE 2 7 The high input impedance and the high DC current gain of the Field Effect 1 2 Transistors result in extremely low current loss through the control gate. DRAIN 3 6 GATE The DC current gain is limited by the gate input leakage current, which is 1 2 specified at 50pA at room temperature. For example, DC beta of the device at a drain current of 5mA at 25C is = 5mA/50pA = 100,000,000. IC 4 5 DRAIN 2 TOP VIEW SAL, PAL PACKAGES FEATURES * IC pin is internally connected. Do not connect externally. Low threshold voltage of 0.7V Low input capacitance Low Vos grades -- 2mV, 5mV, 10mV 12 High input impedance -- 10 typical Negative current (I ) temperature coefficient DS Enhancement-mode (normally off) 9 DC current gain 10 BLOCK DIAGRAM RoHS compliant GATE 1 (2) ORDERING INFORMATION (L suffix denotes lead-free (RoHS)) Operating Temperature Range* DRAIN 1 (3) SOURCE 1 (1) 0C to +70C0C to +70C SUBSTRATE (8) 8-Pin 8-Pin DRAIN 2 (5) SOURCE 2 (7) SOIC Plastic Dip Package Package ALD1101ASAL ALD1101APAL GATE 2 (6) ALD1101BSAL ALD1101BPAL ALD1101SAL ALD1101PAL * Contact factory for high temperature versions. 2021 Advanced Linear Devices, Inc., Vers. 2.2 www.aldinc.com 1 of 7ABSOLUTE MAXIMUM RATINGS Drain-source voltage, V 10V DS Gate-source voltage, V 10V GS Power dissipation 500mW Operating temperature range SAL, PAL packages 0C to +70C Storage temperature range -65C to +150C Lead temperature, 10 seconds +260C CAUTION: ESD Sensitive Device. Use static control procedures in ESD controlled environment. OPERATING ELECTRICAL CHARACTERISTICS T = 25C unless otherwise specified A ALD1101A ALD1101B ALD1101 Test Parameter Symbol Min Typ Max Min Typ Max Min Typ Max Unit Conditions Gate Threshold Voltage V 0.4 0.7 1.0 0.4 0.7 1.0 0.4 0.7 1.0 V I = 10A V = V T DS GS DS Offset Voltage V 2 5 10 mV I = 100A V = V OS DS GS DS V - V GS1 GS2 Gate Threshold TC -1.2 -1.2 -1.2 mV/C VT Temperature Drift On Drain Current I 25 40 25 40 25 40 mA V = V = 5V DS(ON) GS DS Transconductance G 5 10 5 10 5 10 mmho V = 5V I = 10mA fs DS DS Mismatch G 0.5 0.5 0.5 % fs Output G 200 200 200 mho V = 5V I = 10mA OS DS DS Conductance Drain Source R 50 75 50 75 50 75 V = 0.1V V = 5V DS(ON) DS GS ON Resistance Drain Source ON Resistance R 0.5 0.5 0.5 % V = 0.1V V = 5V DS(ON) DS GS Mismatch Drain Source Breakdown BV 10 10 10 V I = 10A V = 0V DSS DS GS Voltage Off Drain Current I 0.1 4 0.1 4 0.1 4 nA V = 10V V = 0V DS(OFF) DS GS 44 4 AT = 125C A Gate Leakage I 1 100 1 100 1 100 pA V = 0V V = 10V GSS DS GS Current 10 10 10 nA T = 125C A Input C 610 6 10 6 10 pF ISS Capacitance ALD1101A/ALD1101B/ALD1101 Advanced Linear Devices 2 of 7