TC74HC595AP(F)

TC74HC595AP/AF TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic TC74HC595AP, TC74HC595AF 8-Bit Shift Register/Latch (3-state) The TC74HC595A is a high speed 8-BIT SHIFT 2 TC74HC595AP REGISTER/LATCH fabricated with silicon gate C MOS technology. It achieve the high speed operation similar to equivalent LSTTL while maintaining the CMOS low power dissipation. The TC74HC595A contains an 8-bit static shift register which feeds an 8-bit storage register. Shift operation is accomplished on the positive going transition of the SCK input. The output register is loaded with the contents of the shift register on the positive going transition of the RCK input. Since RCK and SCK signal are independent, parallel TC74HC595AF outputs can be held stable during the shift operation. And, since the parallel outputs are 3-state, it can be directly connected to 8-bit bus. This register can be used in serial-to-parallel conversion, data receivers, etc. All inputs are equipped with protection circuits against static discharge or transient excess voltage. Features High speed: f = 55 MHz (typ.) at V = 5 V max CC Low power dissipation: I = 4 A (max) at Ta = 25C CC Weight High noise immunity: V = V = 28% V (min) NIH NIL CC DIP16-P-300-2.54A : 1.00 g (typ.) SOP16-P-300-1.27A : 0.18 g (typ.) Output drive capability: 15 LSTTL loads for QA to QH 10 LSTTL loads for QH Symmetrical output impedance: I = I = 6 mA (min) OH OL For QA to QH I = I = 4 mA (min) OH OL For QH Balanced propagation delays: t t pLH pHL Wide operating voltage range: V (opr) = 2 to 6 V CC Pin and function compatible with 74LS595 Pin Assignment Start of commercial production 1986-05 1 2014-03-01 TC74HC595AP/AF IEC Logic Symbol Truth Table Inputs Function SI SCK SCLR RCK G X X X X H QA thru QH outputs disable X X X X L QA thru QH outputs enable X X L X X Shift register is cleared. First stage of S.R. becomes L. Other stages store the data of previous stage, L H X X respectively. First stage of S.R. becomes H. Other stages store the data of previous H H X X stage, respectively. X H X X State of S.R. is not changed. X X X X S.R. data is stored into storage register. X X X X Storage register stage is not changed. X: Dont care 2 2014-03-01