SLG7NT4081VTR

SLG7NT4081 SLG7NT4081 PWROK GENERATOR AND STARTUP LATCHING CIRCUIT General Description Pin Configuration Silego SLG7NT4081 is a low power and small form device. The SoC is housed in a 2.5mm x 2.5mm VDD 1 12 VR ALW ENABLE TDFN package which is optimal for using with small BC ACOK DSW 2 11 SMC SHUTDOWN devices. V3.3A DSW PWRGD 3 10 STARTUP LATCH SET VBAT MON DPWROK 4 9 SMC ONOFF N Features BC ACOK 5 8 PS ON SW N Low Power Consumption PCH DPWROK R 6 7 GND 3.3V Supply Voltage RoHS Compliant / Halogen-Free Thermal Pad TDFN-12 Pb-Free TDFN-12 Package connected to GND TOP VIEW Output Summary 2 Outputs Push Pull 2 Outputs Open Drain Silego Technology, Inc. Rev 1.03 SLG7NT4081 DS r103 Revised July 30, 2013 SLG7NT4081 GP r005 SLG7NT4081 PWROK GENERATOR AND STARTUP LATCHING CIRCUIT Block Diagram Typical Application Circuit +V3.3A DSW +3.3A KBC C1 R1 R2 100nF 100k 100k U1 1 12 VR ALW ENABLE OUT VDD data I/O BC ACOK DSW. 2 11 IN data I data I/O V3.3A DSW PWRGD 3 10 IN data I/O data I/O VBAT MON DPWROK 4 9 SMC ONOFF N IN OUT data I/O data I/O 5 8 data I/O data I/O 6 7 data I/O GND SLG7NT4081 PCH DPWROK R OUT PS ON SW N IN BC ACOK OUT STARTUP LATCH SET IN SMC SHUTDOWN IN SLG7NT4081 DS r103 Page 2