ISLA224S25IR48EV1Z

DATASHEET ISLA224S FN7911 Rev 2.00 Dual 14-Bit, 250/200/125 MSPS JESD204B High Speed Serial Output ADC April 25, 2013 The ISLA224S is a series of low-power, high-performance, Features dual-channel 14-bit, analog-to-digital converters. Designed JESD204A/B High Speed Data Interface with FemtoCharge technology on a standard CMOS process, the series supports sampling rates of up to 250MSPS. The -JESD204A Compliant ISLA224S is part of a pin-compatible family of 12- and 14-bit - JESD204B Device Subclass 0 Compliant dual-channel A/Ds with maximum sample rates ranging from - JESD204B Device Subclass 2 Compatible 125MSPS to 250MSPS and shares the same analog core as - Up to 3 JESD204 Output Lanes Running up to 4.375Gbps Intersil s proven ISLA224P series of ADCs. The family - Highly Configurable JESD204 Transmitter minimizes power consumption while providing state-of-the art dynamic performance, offering an optimal performance-vs- Multiple Chip Time Alignment and Deterministic Latency power trade-off. Support (JESD204B Device Subclass 2) SPI Programmable Debugging Features and Test Patterns Differentiating the ISLA224S from the ISLA224P is its highly configurable, JESD204B-compliant, high speed serial output 48-pin QFN 7mmx7mm Package link. The link offers data rates up to 4.375Gbps per lane and multiple packing modes. It can be configured to use two or Key Specifications three lanes to transmit the conversion data, allowing for SNR 250/200/125MSPS flexibility in the receiver design. The SERDES transmitter also provides deterministic latency and multi-chip time alignment 73.2/74.1/75.1 dBFS f = 30MHz IN support to satisfy an application s complex synchronization 72.4/72.9/73.2 dBFS f = 190MHz requirements. IN SFDR 250/200/125MSPS A serial peripheral interface (SPI) port allows for extensive configurability of the JESD204B transmitter including access 82/91/94 dBc f = 30MHz IN to its built-in link and transport-layer test patterns. The SPI port 84/82/81 dBc f = 190MHz IN also provides control for numerous additional features including the fine gain and offset adjustments of the two ADC Total Power Consumption: 989mW 250MSPS cores as well as the programmable clock divider, enabling 2x and 4x harmonic clocking. Applications The ISLA224S is available in a space-saving 7mmx7mm 48 Ld Radar and Satellite Antenna Array Processing QFN package. The package features a thermal pad for Broadband Communications and Microwave Receivers improved thermal performance and is specified over the full High-Performance Data Acquisition industrial temperature range (-40C to +85C). Communications Test Equipment High-Speed Medical Imaging Pin-Compatible Family SPEED PRODUCT MODEL RESOLUTION (MSPS) AVAILABILITY ISLA224S25 14 250 Now ISLA224S20 14 200 Now ISLA224S12 14 125 Now ISLA222S25 12 250 Now ISLA222S20 12 200 Now ISLA222S12 12 125 Now FIGURE 1. SERDES DATA EYE AT 4.375Gbps FN7911 Rev 2.00 Page 1 of 38 April 25, 2013ISLA224S CLKP CLOCK GENERATION CLKN AINP 14-BIT LANE 2:0 P SHA 250MSPS AINN ADC LANE 2:0 N VREF JESD204 VCM TRANSMITTER BINP 14-BIT SHA 250MSPS BINN ADC VREF + 1.25V SPI CONTROL FIGURE 2. BLOCK DIAGRAM Pin Configuration ISLA224S (48 LD QFN) TOP VIEW 48 47 46 45 44 43 42 41 40 39 38 37 VCM 1 36 OVDD AVDD 2 35 OVSS LANE2N AVSS 3 34 BINP LANE2P 4 33 BINN OVSS 5 32 AVSS 6 31 LANE1N AVSS LANE1P 7 30 AINN 8 29 OVSS AINP LANE0N 9 28 LANE0P AVSS 10 27 AVDD 11 26 OVSS PAD Exposed Paddle DNC 12 25 OVDD 13 14 15 16 17 18 19 20 21 22 23 24 FN7911 Rev 2.00 Page 2 of 38 April 25, 2013 RESETN DNC AVDD NAPSLP DNC AVDD AVDD AVSS AVDD NAPSLP CLKP AVSS (PLL) CLKN CLKDIV SYNC SYNCP SDIO SYNCN SCLK RESETN CSB DNC CSB OVSS (PLL) SDO SCLK SDIO OVDD OVDD (PLL) OVDD SDO (PLL) OVSS OVDD OVSS OVSS (PLL) OVSS OVDD (PLL)