ISLA216P20IRZ

DATASHEET ISLA216P FN7574 Rev.3.0 16-Bit, 250MSPS/200MSPS/130MSPS ADC Jul 6, 2021 The ISLA216P is a family of low power, high performance Features 16-bit analog-to-digital converters. Designed with Renesass Single supply 1.8V operation proprietary FemtoCharge technology on a standard CMOS process, the family supports sampling rates of up to Clock duty cycle stabilizer 250MSPS. The ISLA216P is part of a pin-compatible portfolio 75fs Clock jitter of 12 to 16-bit A/Ds with maximum sample rates ranging from 700MHz Bandwidth 130MSPS to 500MSPS. Programmable built-in test patterns A serial peripheral interface (SPI) port allows for extensive configurability, as well as fine control of various parameters Multi-ADC support such as gain and offset. - SPI Programmable fine gain and offset control Digital output data is presented in selectable LVDS or CMOS - Support for multiple ADC synchronization formats. The ISLA216P is available in a 72-contact QFN - Optimized output timing package with an exposed paddle. Operating from a 1.8V Nap and sleep modes supply, performance is specified over the full industrial - 200s Sleep wake-up time temperature range (-40C to +85C). Data output clock Key Specifications DDR LVDS-compatible or LVCMOS outputs SNR 250/200/130MSPS Selectable Clock Divider - 75.0/76.6/77.5dBFS f = 30MHz IN Applications - 72.1/72.6/72.4dBFS f = 363MHz IN SFDR 250/200/130MSPS Radar array processing - 87/91/96dBc f = 30MHz IN Software defined radios - 81/80/82dBc f = 363MHz IN Broadband communications Total Power Consumption = 786mW 250MSPS High-performance data acquisition Communications test equipment Pin-Compatible Family SPEED MODEL RESOLUTION (MSPS) ISLA216P25 16 250 ISLA216P20 16 200 CLKP CLKOUTP ISLA216P13 16 130 CLOCK MANAGEMENT CLKN CLKOUTN ISLA214P50 14 500 ISLA214P25 14 250 ISLA214P20 14 200 VINP 16-BIT ISLA214P13 14 130 SHA 250 MSPS D 14:0 P VINN ADC ISLA212P50 12 500 D 14:0 N DIGITAL ERROR ISLA212P25 12 250 + CORRECTION VCM ISLA212P20 12 200 SPI CONTROL ISLA212P13 12 130 FN7574 Rev.3.0 Page 1 of 33 Jul 6, 2021 2011 Renesas Electronics AVSS AVDD NAPSLP RESETN CSB SCLK SDIO SDO CLKDIV CLKDIVRSTP CLKDIVRSTN RLVDS OVSS OVDDISLA216P Table of Contents Pin-Compatible Family . 1 Pin Configuration - LVDS MODE 3 Pin Descriptions - 72 Ld QFN, LVDS Mode . 3 Pin Configuration - CMOS MODE . 5 Pin Descriptions - 72 Ld QFN, CMOS Mode 5 Ordering Information 6 Absolute Maximum Ratings . 7 Thermal Information . 7 Timing Diagrams . 10 Typical Performance Curves . 12 Theory of Operation . 15 Functional Description . 15 Power-On Calibration . 15 User Initiated Reset 16 Temperature Calibration . 16 Analog Input 17 Clock Input . 18 Jitter . 18 Voltage Reference . 19 Digital Outputs 19 Power Dissipation . 19 Nap/Sleep 19 Data Format 19 Clock Divider Synchronous Reset . 20 Serial Peripheral Interface 23 SPI Physical Interface 23 SPI Configuration 23 Device Information 24 Device Configuration/Control 24 Global Device Configuration/Control . 25 Digital Temperature Sensor . 26 SPI Memory Map . 27 Equivalent Circuits . 30 A/D Evaluation Platform . 31 Layout Considerations 31 Split Ground and Power Planes 31 Clock Input Considerations 31 Exposed Paddle . 31 Bypass and Filtering . 31 LVDS Outputs . 31 LVCMOS Outputs 31 Unused Inputs 31 Definitions 31 Revision History 32 Package Outline Drawing 33 FN7574 Rev.3.0 Page 2 of 33 Jul 6, 2021