Product Information

8T79S308NLGI

8T79S308NLGI electronic component of Renesas

Datasheet
Clock Buffer 8T79S308 1:8 UNIVERSAL DIFFERENTIAL FANOUT BUFFER

Manufacturer: Renesas
This product is classified as Large/Heavy, additional shipping charges may apply. A customer service representative may contact you after ordering to confirm exact shipping charges



Price (USD)

1: USD 16.1334 ea
Line Total: USD 16.1334

219 - Global Stock
Ships to you between
Thu. 11 Apr to Mon. 15 Apr
MOQ: 1  Multiples: 1
Pack Size: 1
Availability Price Quantity
127 - Global Stock


Ships to you between Thu. 11 Apr to Mon. 15 Apr

MOQ : 1
Multiples : 1

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8T79S308NLGI
Renesas

1 : USD 13.7425
10 : USD 12.788
25 : USD 12.2475
100 : USD 11.0975
250 : USD 10.557
490 : USD 10.028
980 : USD 9.591
2940 : USD 9.522
5390 : USD 9.223

     
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1:8 Universal Differential Fanout 8T79S308 Datasheet Buffer Description Features High-performance, flexible clock/data/1PPS fanout buffer The 8T79S308 is a fully integrated signal fanout buffer for high-performance, low additive phase noise applications. The Low phase noise floor: -160dBc/Hz (156.256MHz clock) main function of the device is the distribution and fanout of Integrated phase noise of < 65fs RMS typical (12kHz20MHz) high-frequency clocks or low-frequency synchronization signals. Flexible input selection The 8T79S308 is optimized to deliver very low phase noise clocks 1:8 Fanout modes and precise, low-skew outputs, low device-to-device skew Dual 1:4 Buffer fanout modes characteristics and fast output rise/fall times help the system Eight differential outputs, organized in two banks of four design to achieve deterministic clock phase relationship across outputs devices. Low-power LVPECL/LVDS outputs support DC and AC The device distributes the input signals (IN 0, IN 1) to two fanout coupling and LVPECL, LVDS line terminations techniques banks. A input select logic allows the device to operate as 2 Individually configured outputs through an I C interface 1:8 buffer, dual 1:4 buffers, and to cross the input signals. LVPECL/LVDS output style, HCSL compatible (AC-coupled) The propagation delay in both outputs banks is designed for equal Output amplitude delay to support fixed phase relationships between both banks. All Output enable outputs are very flexible in LVPECL/LVDS output style configuration, output signal termination, and allow both DC and Supported clock frequency range: 0 to 3GHz AC coupling. Outputs can be individually disabled through a serial Core and output supply voltage modes: interface. 3.3V core, 3.3V, 2.5V, and 1.8V output supply The device is packaged in a lead-free (RoHS 6) 40-VFQFPN 2.5V core, 2.5V, and 1.8V output supply package. The extended temperature range supports wireless 2 Selectable I C I/O interface voltage: 1.8V and VDD infrastructure, telecommunication, and networking end equipment Integrated low dropout regulators (LDOs) for excellent power requirements. The 8T79S308 is a member of the supply noise rejection high-performance clock family from IDT. Package: 6 6 mm 40-VFQFPN Temperature range: -40C to +105C Block Diagram Typical Applications IN 0 QA0 nIN 0 nQA0 Wireless infrastructure applications: GSM, WCDMA, LTE, 50 50 QA1 VT 0 nQA1 LTE-A IN 1 QA2 Ideal clock driver for jitter-sensitive ADC and DAC circuits nIN 1 nQA2 50 50 Low phase noise clock generation VT 1 QA3 nQA3 Ethernet line cards XSEL 1:0 Bank A Radar and imaging Instrumentation and medical QB0 nQB0 POD OE QB1 SDA nQB1 2 I C SCL Output QB2 Enable VSEL I2C nQB2 Register VSEL VDD QB3 nQB3 ADR 2:0 Bank B 2018 Integrated Device Technology, Inc 1 August 10, 20188T79S308 Datasheet Contents Description 1 Block Diagram . 1 Features 1 Typical Applications . 1 Pin Assignments 3 Pin Descriptions 3 Principles of Operation . 5 Overview . 5 Voltage Supply 5 Pin Controlled Settings . 6 Input Signal Selection . 6 Configuration Registers 7 Device Information Registers . 8 Device Configuration Registers . 9 Serial Interface 10 I2C Interface . 10 Absolute Maximum Ratings 12 Pin Characteristics . 12 DC Characteristics . 13 AC Characteristics . 17 Phase Noise Plots . 19 Application Information 21 Termination for Q, nQ LVDS Outputs 22 AC Termination for Q, nQ Outputs 22 Termination for Q, nQ LVPECL Outputs 23 Termination for Q, nQ LVPECL Outputs AC-Coupled into HCSL-Receiver . 23 Input Interface Circuits . 24 Thermal Characteristics . 26 Temperature Considerations . 26 Package Outline Drawings . 28 Marking Diagram 28 Ordering Information . 28 Glossary . 29 Revision History . 29 2018 Integrated Device Technology, Inc 2 August 10, 2018

Tariff Desc

8542.39.23 No ..Linear/analogue and peripheral integrated circuits, timers, voltage regulators, A/D and D/A converters, telecommunication and modem integrated circuits, other than board level products Free

Electronic integrated circuits- Processors and controllers, whether or not combined with memories, converters, logic circuits, amplifiers, clock and timing circuits, or other circuits
CEL (RENESAS)
ID4
IDT
IDT, Integrated Device Technology Inc
INTEGRATED DEVICE
INTEGRATED DEVICE TECHNOLOGY
INTEGRATED DEVICES TECH AID
Intersil
INTERSIL - FGC
Intersil(Renes as Electronics)
Intersil(Renesas Electronics)
ITS
REA
RENESAS
RENESAS (IDT)
RENESAS (INTERSIL)
Renesas / IDT
Renesas / Intersil
Renesas Electronics
Renesas Electronics America
RENESAS TECHNOLOGY

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