Product Information

NB7L585MNG

NB7L585MNG electronic component of ON Semiconductor

Datasheet
Clock Drivers & Distribution 2.5/3.3V DIFF MUX

Manufacturer: ON Semiconductor
This product is classified as Large/Heavy, additional shipping charges may apply. A customer service representative may contact you after ordering to confirm exact shipping charges



Price (USD)

1: USD 12.443 ea
Line Total: USD 12.443

293 - Global Stock
Ships to you between
Wed. 10 Apr to Fri. 12 Apr
MOQ: 1  Multiples: 1
Pack Size: 1
Availability Price Quantity
293 - Global Stock


Ships to you between Wed. 10 Apr to Fri. 12 Apr

MOQ : 1
Multiples : 1

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NB7L585MNG
ON Semiconductor

1 : USD 12.443
10 : USD 11.5805
25 : USD 11.3045
50 : USD 11.155
74 : USD 9.545
296 : USD 9.085
518 : USD 8.671
1036 : USD 8.671

     
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NB7L585 2.5V / 3.3V Differential 2:1 Mux Input to 1:6 LVPECL Clock/Data Fanout Buffer / Translator NB7L585 Exposed Pad (EP) Table 1. INPUT SELECT FUNCTION TABLE SEL* CLK Input Selected 32 31 30 29 28 27 26 25 0 IN0 IN0 1 24 GND 1 IN1 VT0 2 23 VCC *Defaults HIGH when left open. VREFAC0 3 22 Q2 IN0 Q2 4 21 NB7L585 IN1 Q3 5 20 VT1 6 19 Q3 VREFAC1 7 18 VCC IN1 GND 8 17 910 11 12 13 14 15 16 Figure 2. Pinout: QFN32 (Top View) Table 2. PIN DESCRIPTION Pin Number Pin Name I/O Pin Description 1,4 IN0, IN0 LVPECL, CML, Noninverted, Inverted, Differential Data Inputs internally biased to V /2 CC 5,8 IN1, IN1 LVDS Input 2,6 VT0, VT1 Internal 100 Centertapped Termination Pin for IN0 / IN0 and IN1 / IN1 31 SEL LVTTL/LVCMOS Input Select pin LOW for IN0 Inputs, HIGH for IN1 Inputs defaults HIGH when left Input open 10 NC No Connect 11, 16, 18 V Positive Supply Voltage. All V pins must be connected to the positive power supply CC CC 23, 25, 30 for correct DC and AC operation. 29, 28 Q0, Q0 LVPECL Output Noninverted, Inverted Differential Outputs Note 1. 27, 26 Q1, Q1 22, 21 Q2,Q2 20, 19 Q3, Q3 15, 14 Q4, Q4 13, 12 Q5, Q5 9, 17, 24, 32 GND Negative Supply Voltage, connected to Ground 3 VREFAC0 Output Voltage Reference for CapacitorCoupled Inputs 7 VREFAC1 EP The Exposed Pad (EP) on the QFN32 package bottom is thermally connected to the die for improved heat transfer out of package. The exposed pad must be attached to a heatsinking conduit. The pad is electrically connected to the die, and must be elec- trically and thermally connected to GND on the PC board. 1. In the differential configuration when the input termination pins (VT0, VT1) are connected to a common termination voltage or left open, and if no signal is applied on INn/INn input, then the device will be susceptible to selfoscillation. 2. All V and GND pins must be externally connected to a power supply for proper operation. CC

Tariff Desc

8542.39.23 No ..Linear/analogue and peripheral integrated circuits, timers, voltage regulators, A/D and D/A converters, telecommunication and modem integrated circuits, other than board level products Free

Electronic integrated circuits- Processors and controllers, whether or not combined with memories, converters, logic circuits, amplifiers, clock and timing circuits, or other circuits
Aptina / ON Semiconductor
FAIRCHILD
FAIRCHILD (ON SEMICONDUCTOR)
Fairchild Semiconductor
FS8
FSC
ON
ON SEMI
ON Semicon
ON SEMICONDUCTOR
ON SEMICONDUCTOR (FAIRCHILD)
ON Semiconductor / Fairchild
ON4
ON5
onsemi
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