NB2305A
3.3 V Zero Delay
Clock Buffer
The NB2305A is a versatile, 3.3 V zero delay buffer designed to
distribute highspeed clocks. It accepts one reference input and drives
out five lowskew clocks. It is available in a 8 pin package.
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The 1H version of the NB2305A operates at up to 133 MHz, and
has higher drive than the 1 devices. All parts have onchip PLLs that
MARKING
lock to an input clock on the REF pin. The PLL feedback is onchip
DIAGRAMS*
and is obtained from the CLKOUT pad.
Multiple NB2305A devices can accept the same input clock and
8
8
distribute it. In this case the skew between the outputs of the two
XXXX
1
devices is guaranteed to be less than 700 ps.
ALYW
All outputs have less than 200 ps of cycletocycle jitter. The input SOIC8
D SUFFIX 1
and output propagation delay is guaranteed to be less than 350 ps, and
CASE 751
the output to output skew is guaranteed to be less than 250 ps.
The NB2305A is available in two different configurations, as shown
8
in the ordering information table. The NB2305AI is the base part. The
8
XXX
NB2305AI1H is the high drive version of the 1 and its rise and fall
YWW
times are much faster than 1 part.
A
1
1
Features
TSSOP8
DT SUFFIX
15 MHz to 133 MHz Operating Range, Compatible with CPU and
CASE 948S
PCI Bus Frequencies
Zero Input Output Propagation Delay
XXXX = Device Code
Multiple LowSkew Outputs
A = Assembly Location
L = Wafer Lot
OutputOutput Skew Less than 250 ps
Y = Year
DeviceDevice Skew Less than 700 ps
W = Work Week
= PbFree Package
One Input Drives 5 Outputs
Less than 200 ps CycletoCycle Jitter is Compatible with Pentium
*For additional marking information, refer to
Based Systems
Application Note AND8002/D.
Accepts Spread Spectrum Clock at the Input
Available in 8 Pin, 150 mil SOIC Package and 8 Pin TSSOP 4.4 mm
3.3 V Operation, Advanced 0.35 CMOS Technology
ORDERING INFORMATION
Guaranteed Across Commercial and Industrial Temperature Ranges
See detailed ordering, marking and shipping information in the
package dimensions section on page 6 of this data sheet.
These are PbFree Devices
Semiconductor Components Industries, LLC, 2015
1 Publication Order Number:
May, 2015 Rev. 11 NB2305A/DNB2305A
PLL CLKOUT
REF
REF 1 8
CLKOUT
CLK1
2
CLK2 7 CLK4
NB2305A
CLK2
CLK1 3 6 V
DD
CLK3
GND 4 5 CLK3
CLK4
Figure 1. Block Diagram Figure 2. Pin Configuration
Table 1. PIN DESCRIPTION
Pin # Pin Name Description
1 REF (Note1) Input reference frequency, 5 V tolerant input.
2 CLK2 (Note 2) Buffered clock output.
3 CLK1 (Note 2) Buffered clock output.
4 GND Ground.
5 CLK3 (Note 2) Buffered clock output.
6 V 3.3 V supply.
DD
7 CLK4 (Note 2) Buffered clock output.
8 CLKOUT (Note 2) Buffered clock output, internal feedback on this pin.
1. Weak pulldown.
2. Weak pulldown on all outputs.
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2