Product Information

MC10EP32DG

MC10EP32DG electronic component of ON Semiconductor

Datasheet
Multipliers / Dividers 3.3V/5V ECL Divide By 2 Divider

Manufacturer: ON Semiconductor
This product is classified as Large/Heavy, additional shipping charges may apply. A customer service representative may contact you after ordering to confirm exact shipping charges



Price (USD)

2: USD 4.9757 ea
Line Total: USD 9.9514

0 - Global Stock
MOQ: 2  Multiples: 1
Pack Size: 1
Availability Price Quantity
0 - Global Stock


Ships to you between Fri. 05 Apr to Thu. 11 Apr

MOQ : 98
Multiples : 1

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MC10EP32DG
ON Semiconductor

98 : USD 8.4412
100 : USD 8.4
250 : USD 8.3575
500 : USD 8.315
1000 : USD 8.2725
2000 : USD 8.2287
2500 : USD 8.185
3000 : USD 8.14
5000 : USD 8.095
10000 : USD 8.05

0 - Global Stock


Ships to you between Fri. 05 Apr to Thu. 11 Apr

MOQ : 3
Multiples : 3

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MC10EP32DG
ON Semiconductor

3 : USD 5.1129
20 : USD 4.4077
75 : USD 4.4077
250 : USD 4.2313
1000 : USD 4.2313

0 - Global Stock


Ships to you between Fri. 05 Apr to Thu. 11 Apr

MOQ : 196
Multiples : 196

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MC10EP32DG
ON Semiconductor

196 : USD 6.9276

0 - Global Stock


Ships to you between Thu. 11 Apr to Mon. 15 Apr

MOQ : 1
Multiples : 1

Stock Image

MC10EP32DG
ON Semiconductor

1 : USD 9.545
10 : USD 8.7745
98 : USD 7.1415
196 : USD 6.578

0 - Global Stock


Ships to you between Fri. 05 Apr to Thu. 11 Apr

MOQ : 2
Multiples : 1

Stock Image

MC10EP32DG
ON Semiconductor

2 : USD 4.9149
10 : USD 4.6984
25 : USD 4.5805
100 : USD 4.4889

0 - Global Stock


Ships to you between Fri. 05 Apr to Thu. 11 Apr

MOQ : 2
Multiples : 1

Stock Image

MC10EP32DG
ON Semiconductor

2 : USD 4.9757
10 : USD 4.3838
25 : USD 4.2276
50 : USD 4.1431

     
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3.3 V/5 VECL 2 Divider MC10EP32, MC100EP32 Description The MC10/100EP32 is an integrated 2 divider with differential CLK inputs. The V pin, an internally generated voltage supply, is available to BB www.onsemi.com this device only. For single-ended input conditions, the unused differential input is connected to V as a switching reference voltage. BB V may also rebias AC coupled inputs. When used, decouple V BB BB 8 8 and V via a 0.01 F capacitor and limit current sourcing or sinking CC 1 1 to 0.5 mA. When not used, V should be left open. BB The reset pin is asynchronous and is asserted on the rising edge. DFN8 SOIC8NB TSSOP8 MN SUFFIX D SUFFIX DT SUFFIX Upon power-up, the internal flip-flops will attain a random state the CASE 75107 CASE 948R02 CASE 506AA reset allows for the synchronization of multiple EP32s in a system. The 100 Series contains temperature compensation. Features 350 ps Typical Propagation Delay MARKING DIAGRAMS* Maximum Frequency > 4 GHz Typical (Figure 3) 8 8 PECL Mode Operating Range: HEP32 HP32 V = 3.0 V to 5.5 V with V = 0 V CC EE ALYW ALYW NECL Mode Operating Range: 1 V = 0 V with V = 3.0 V to 5.5 V 1 CC EE Open Input Default State 8 8 Safety Clamp on Inputs KEP32 KP32 Q Output Will Default LOW with Inputs Open or at V EE ALYW ALYW These Devices are Pb-Free, Halogen Free and are RoHS Compliant 14 1 1 H = MC10 A = Assembly Location K = MC100 L = Wafer Lot 3K = MC100 Y = Year M = Date Code W = Work Week = Pb-Free Package (Note: Microdot may be in either location) *For additional marking information, refer to Application Note AND8002/D. ORDERING INFORMATION See detailed ordering and shipping information on page 8 of this data sheet. Semiconductor Components Industries, LLC, 2016 1 Publication Order Number: April, 2021 Rev. 13 MC10EP32/D 3K M MC10EP32, MC100EP32 Table 1. PIN DESCRIPTION RESET 1 8 V CC Pin Function R CLK, CLK* ECL Clock Inputs Reset* ECL Asynchronous Reset CLK 2 7 Q V Reference Voltage Output BB 2 Q, Q ECL Data Outputs V Positive Supply CLK 3 6 Q CC V Negative Supply EE EP (DFN8 only) Thermal exposed pad must be connected to a sufficient thermal V45 V BB EE conduit. Electrically connect to the most negative supply (GND) or leave uncon- nected, floating open. Figure 1. 8-Lead Pinout (Top View) and Logic *Pins will default LOW when left open. Diagram Table 2. TRUTH TABLE CLK CLK RESET Q Q X X Z L H Z Z L F F Z = LOW to HIGH Transition Z = HIGH to LOW Transition F = Divide by 2 Function CLK t RR RESET Q Figure 2. Timing Diagram Table 3. ATTRIBUTES Characteristics Value Internal Input Pulldown Resistor 75 k Internal Input Pullup Resistor N/A ESD Protection Human Body Model > 4 kV Machine Model > 200 V Charged Device Model > 2 kV Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1) Pb-Free Pkg SOIC8NB Level 1 TSSOP8 Level 3 DFN8 Level 1 Flammability Rating Oxygen Index: 28 to 34 UL 94 V0 0.125 in Transistor Count 78 Devices Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 1. For additional information, see Application Note AND8003/D. www.onsemi.com 2

Tariff Desc

8542.39.23 No ..Linear/analogue and peripheral integrated circuits, timers, voltage regulators, A/D and D/A converters, telecommunication and modem integrated circuits, other than board level products Free

Electronic integrated circuits- Processors and controllers, whether or not combined with memories, converters, logic circuits, amplifiers, clock and timing circuits, or other circuits
Aptina / ON Semiconductor
FAIRCHILD
FAIRCHILD (ON SEMICONDUCTOR)
Fairchild Semiconductor
FS8
FSC
ON
ON SEMI
ON Semicon
ON SEMICONDUCTOR
ON SEMICONDUCTOR (FAIRCHILD)
ON Semiconductor / Fairchild
ON4
ON5
onsemi
ON-SEMI
onsemi / Fairchild
OOF
Xsens / Fairchild

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