SPC5605BF1VLU6

NXP Semiconductors Document Number: MPC5607B Rev. 9, 11/2017 Data Sheet: Technical Data MPC5607B MPC5607B Microcontroller Data Sheet 144 LQFP (20 mm x 20 mm) 208 MAPBGA (17 mm x 17 mm) 100 LQFP (14 mm x 14mm) LQFP176 (24 mm x 24 mm) Features Up to 10 serial communication interface (LINFlex) Single issue, 32-bit CPU core complex (e200z0h) modules Compliant with the Power Architecture technology Up to 6 enhanced full CAN (FlexCAN) modules with embedded category configurable buffers 2 Enhanced instruction set allowing variable length 1 inter-integrated circuit (I C) interface module encoding (VLE) for code size footprint reduction. Up to 149 configurable general purpose pins supporting With the optional encoding of mixed 16-bit and input and output operations (package dependent) 32-bit instructions, it is possible to achieve Real-Time Counter (RTC) significant code size footprint reduction. Clock source from internal 128 kHz or 16 MHz oscillator Up to 1.5 MB on-chip code flash memory supported with supporting autonomous wakeup with 1 ms resolution with the flash memory controller maximum timeout of 2 seconds 64 (4 16) KB on-chip data flash memory with ECC Optional support for RTC with clock source from external Up to 96 KB on-chip SRAM 32 kHz crystal oscillator, supporting wakeup with 1 sec Memory protection unit (MPU) with 8 region descriptors resolution and maximum timeout of 1 hour and 32-byte region granularity on certain family members Up to 8 periodic interrupt timers (PIT) with 32-bit counter (Refer to Table 1 for details.) resolution Interrupt controller (INTC) capable of handling 204 Nexus development interface (NDI) per IEEE-ISTO selectable-priority interrupt sources 5001-2003 Class Two Plus Frequency modulated phase-locked loop (FMPLL) Device/board boundary scan testing supported per Joint Crossbar switch architecture for concurrent access to Test Action Group (JTAG) of IEEE (IEEE 1149.1) peripherals, Flash, or RAM from multiple bus masters On-chip voltage regulator (VREG) for regulation of 16-channel eDMA controller with multiple transfer input supply for all internal levels request sources using DMA multiplexer Boot assist module (BAM) supports internal Flash programming via a serial link (CAN or SCI) Timer supports I/O channels providing a range of 16-bit input capture, output compare, and pulse width modulation functions (eMIOS) 2 analog-to-digital converters (ADC): one 10-bit and one 12-bit Cross Trigger Unit to enable synchronization of ADC conversions with a timer event from the eMIOS or PIT Up to 6 serial peripheral interface (DSPI) modules NXP reserves the right to change the production detail specifications as may be required to permit improvements in the design of its products.Table of Contents 1 Introduction 3 4.9.1 Program/erase characteristics . 63 1.1 Description .3 4.9.2 Flash power supply DC characteristics 64 2 Block diagram 5 4.9.3 Start-up/Switch-off timings 65 3 Package pinouts and signal descriptions .8 4.10 Electromagnetic compatibility (EMC) characteristics 65 3.1 Package pinouts .8 4.10.1Designing hardened software to avoid noise 3.2 Pad configuration during reset phases11 problems 65 3.3 Pad configuration during standby mode exit .12 4.10.2 Electromagnetic interference (EMI) . 66 3.4 Voltage supply pins 12 4.10.3 Absolute maximum ratings (electrical sensitivity)66 3.5 Pad types .13 4.11 Fast external crystal oscillator (4 to 16 MHz) electrical 3.6 System pins .13 characteristics . 67 3.7 Functional port pins .14 4.12 Slow external crystal oscillator (32 kHz) electrical 3.8 Nexus 2+ pins 34 characteristics . 70 4 Electrical characteristics .34 4.13 FMPLL electrical characteristics . 72 4.1 Parameter classification 35 4.14 Fast internal RC oscillator (16MHz) electrical 4.2 NVUSRO register .35 characteristics . 73 4.2.1 NVUSRO PAD3V5V field description 35 4.15 Slow internal RC oscillator (128kHz) electrical 4.2.2 NVUSRO OSCILLATOR MARGIN field description characteristics . 74 36 4.16 ADC electrical characteristics . 75 4.2.3 NVUSRO WATCHDOG EN field description 36 4.16.1 Introduction . 75 4.3 Absolute maximum ratings 36 4.16.2 Input impedance and ADC accuracy 76 4.4 Recommended operating conditions 37 4.16.3 ADC electrical characteristics . 81 4.5 Thermal characteristics .40 4.17 On-chip peripherals . 86 4.5.1 External ballast resistor recommendations 40 4.17.1 Current consumption 86 4.5.2 Package thermal characteristics 40 4.17.2 DSPI characteristics . 88 4.5.3 Power considerations .41 4.17.3 Nexus characteristics 94 4.6 I/O pad electrical characteristics 42 4.17.4 JTAG characteristics . 95 4.6.1 I/O pad types .42 5 Package characteristics . 97 4.6.2 I/O input DC characteristics 42 5.1 Package mechanical data 97 4.6.3 I/O output DC characteristics .43 5.1.1 176 LQFP . 97 4.6.4 Output pin transition times .46 5.1.2 144 LQFP 100 4.6.5 I/O pad current specification .47 5.1.3 100 LQFP 102 4.6.6 RESET electrical characteristics 54 5.1.4 208 MAPBGA . 105 4.7 Power management electrical characteristics 57 6 Ordering information 107 4.7.1 Voltage regulator electrical characteristics 57 7 Revision history 109 4.7.2 Low voltage detector electrical characteristics .59 4.8 Power consumption 61 4.9 Flash memory electrical characteristics 63 MPC5607B Microcontroller Data Sheet, Rev. 9 2 NXP Semiconductors