S9S08RN48W1CLF

Document Number: S9S08RN60 Freescale Semiconductor Rev. 1, 01/2014 Data Sheet: Technical Data S9S08RN60 S9S08RN60 Series Data Sheet Supports: S9S08RN60, S9S08RN48 and S9S08RN32 Features Development support 8-Bit S08 central processor unit (CPU) Single-wire background debug interface Up to 20 MHz bus at 2.7 V to 5.5 V across Breakpoint capability to allow three breakpoints temperature range of -40 C to 125 C setting during in-circuit debugging Supporting up to 40 interrupt/reset sources On-chip in-circuit emulator (ICE) debug module Supporting up to four-level nested interrupt containing two comparators and nine trigger modes On-chip memory Peripherals Up to 60 KB flash read/program/erase over full ACMP - one analog comparator with both positive operating voltage and temperature and negative inputs separately selectable interrupt Up to 256 byte EEPROM with ECC 2-byte erase on rising and falling comparator output filtering sector EEPROM program and erase while executing ADC - 16-channel, 12-bit resolution 2.5 s code from flash conversion time data buffers with optional Up to 4096 byte random-access memory (RAM) watermark automatic compare function internal Flash and RAM access protection bandgap reference channel operation in stop mode Power-saving modes optional hardware trigger One low-power stop mode reduced power wait CRC - programmable cyclic redundancy check mode module Peripheral clock enable register can disable clocks to FTM - three flex timer modulators modules unused modules, reducing currents allows clocks to including one 6-channel and two 2-channel ones remain enabled to specific peripherals in stop3 mode 16-bit counter each channel can be configured for input capture, output compare, edge- or center- Clocks aligned PWM mode Oscillator (XOSC) - loop-controlled Pierce IIC - One inter-integrated circuit module up to 400 oscillator crystal or ceramic resonator kbps multi-master operation programmable slave Internal clock source (ICS) - containing a frequency- address supporting broadcast mode and 10-bit locked-loop (FLL) controlled by internal or external addressing reference precision trimming of internal reference MTIM - Two modulo timers with 8-bit prescaler and allowing 1% deviation across temperature range of 0 overflow interrupt C to 70 C and -40 C to 85 C, 1.5% deviation RTC - 16-bit real timer counter (RTC) across temperature range of -40 C to 105 C, and SCI - three serial communication interface (SCI/ 2% deviation across temperature range of -40 C to UART) modules optional 13-bit break full duplex 125 C up to 20 MHz non-return to zero (NRZ) LIN extension support SPI - one 8-bit and one 16-bit serial peripheral System protection interface (SPI) modules full-duplex or single-wire Watchdog with independent clock source bidirectional master or slave mode Low-voltage detection with reset or interrupt TSI - supporting up to 16 external electrodes selectable trip points configurable software or hardware scan trigger fully Illegal opcode detection with reset support freescale touch sensing software library Illegal address detection with reset capability to wake MCU from stop3 mode Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. 2014 Freescale Semiconductor, Inc.Input/Output Up to 55 GPIOs including one output-only pin Two 8-bit keyboard interrupt modules (KBI) Two true open-drain output pins Eight, ultra-high current sink pins supporting 20 mA source/sink current Package options 64-pin LQFP 48-pin LQFP 32-pin LQFP S9S08RN60 Series Data Sheet Data Sheet, Rev. 1, 01/2014. 2 Freescale Semiconductor, Inc.