PCF8583P/F5,112

PCF8583 Clock and calendar with 240 x 8-bit RAM Rev. 06 6 October 2010 Product data sheet 1. General description 1 The PCF8583 is a clock and calendar chip, based on a 2048 bit static CMOS RAM organized as 256 words by 8 bits. Addresses and data are transferred serially via the 2 two-line bidirectional I C-bus. The built-in word address register is incremented automatically after each written or read data byte. Address pin A0 is used for programming the hardware address, allowing the connection of two devices to the bus without additional hardware. The built-in 32.768 kHz oscillator circuit and the first 8 bytes of the RAM are used for the clock, calendar, and counter functions. The next 8 bytes can be programmed as alarm registers or used as free RAM space. The remaining 240 bytes are free RAM locations. 2. Features and benefits 2 I C-bus interface operating supply voltage: 2.5 V to 6 V Clock operating supply voltage 1.0 V to 6.0 V at 0 Cto+70 C 240 8-bit low-voltage RAM Data retention voltage: 1.0 V to 6.0 V Operating current (at f = 0 Hz): max 50 A SCL Clock function with four year calendar Universal timer with alarm and overflow indication 24 hour or 12 hour format 32.768 kHz or 50 Hz time base 2 Serial input and output bus (I C-bus) Automatic word address incrementing Programmable alarm, timer, and interrupt function Slave addresses: A1h or A3h for reading, A0h or A2h for writing 1. The definition of the abbreviations and acronyms used in this data sheet can be found in Section 14.PCF8583 NXP Semiconductors Clock and calendar with 240 x 8-bit RAM 3. Ordering information Table 1. Ordering information Type number Package Name Description Version PCF8583P DIP8 plastic dual in-line package 8 leads (300 mil) SOT97-1 PCF8583T SO8 plastic small outline package 8 leads SOT176-1 body width 7.5 mm PCF8583BS HVQFN20 plastic thermal enhanced very thin quad flat package SOT662-1 no leads 20 terminals body 5 5 0.85 mm 4. Marking Table 2. Marking codes Type number Marking code PCF8583P PCF8583P PCF8583T 8583T PCF8583BS 8583S 5. Block diagram 00h control/status OSCI DIVIDER 01h hundredth second OSCILLATOR OSCO 02h seconds 03h minutes INT 04h hours year/date 05h V DD CONTROL POWER-ON 06h weekdays/months LOGIC RESET V SS 07h timer alarm control 08h PCF8583 to alarm or RAM 0Fh A0 2 I C-BUS ADDRESS SCL RAM INTERFACE REGISTER FFh (240 x 8 bit) SDA 013aaa365 Fig 1. Block diagram of PCF8583 PCF8583 All information provided in this document is subject to legal disclaimers. NXP B.V. 2010. All rights reserved. Product data sheet Rev. 06 6 October 2010 2 of 37