P1014NSE5HHB

Freescale Semiconductor Document Number: P1014EC Data Sheet: Advance Information Rev. 4, 05/2014 P1014 P1014 QorIQ Integrated Processor Hardware TePBGA1-425 19 mm x 19 mm Specifications The following list provides an overview of the P1014 feature Programmable interrupt controller (PIC) compliant with set: OpenPIC standard One 4-channel DMA controller High-performance 32-bit Book E-enhanced core based on 2 Two I C interfaces the Power Architecture technology: Four UART interfaces 36-bit physical addressing Integrated Flash controller (IFC) Double-precision floating-point support TDM 32-Kbyte L1 instruction cache and 32-Kbyte L1 data 16 general-purpose I/O signals cache Operating temperature (Ta - T ) range: 0105 C (standard) 400- to 1000-MHz clock frequency j and 40 C to 105 C (extended) 256-Kbyte L2 cache with ECC. Also configurable as 19 19 mm 425-ball wirebond TePBGA-1 package with SRAM and stashing memory 0.8 mm pitch Two enhanced three-speed Ethernet controllers (eTSECs) 10/100/1000 Mbps support TCP/IP acceleration, quality of service, and classification capabilities IEEE Std 1588 support RGMII, SGMII eTSEC1 supports both RGMII/SGMII interfaces and eTSEC2 support SGMII interface High-speed interfaces supporting the following multiplexing options: Two PCI Express 1.1 interfaces Two SATA Revision 2.0 interfaces Five lanes of high-speed serial interfaces to be shared between PCI Express, SATA, and SGMII High-speed USB controller (USB 2.0) Host and device support On-chip USB 2.0 high-speed PHY Enhanced host controller interface (EHCI) ULPI interface Enhanced secure digital host controller (SD/MMC) Enhanced serial peripheral interface (eSPI) Integrated security engine (ULE CAAM) Protocol support includes DES, AES, RNG, CRC, MDE, PKE, SHA, and MD5. DDR3/DDR3L SDRAM memory controller supports and 16-bit with ECC This document contains information on a new product. Specifications and information herein are subject to change without notice. Freescale Semiconductor, Inc., 2011-2014. All rights reserved.Table of Contents 1 Pin assignments and reset states .4 2.21 PCI Express . 76 1.1 Ball layout diagrams 4 2.22 Serial ATA (SATA) 80 1.2 Pinout assignments 11 3 Hardware design considerations 84 2 Electrical characteristics .21 3.1 System clocking 84 2.1 Overall DC electrical characteristics .21 3.2 Supply power default setting 87 2.2 Power sequencing .25 3.3 Power supply design and sequencing . 88 2.3 Power-down Requirements 25 3.4 Decoupling recommendations . 89 2.4 Reset Initialization .25 3.5 SerDes block power supply decoupling 2.5 Power-on ramp rate 26 recommendations 89 2.6 Power characteristics 26 3.6 Connection recommendations . 89 2.7 Input clocks 28 3.7 Pull-up and pull-down resistor requirements 89 2.8 DDR3, and DDR3L SDRAM controller .31 3.8 Output buffer DC impedance . 90 2.9 eSPI .38 3.9 Configuration pin muxing . 90 2.10 DUART .39 3.10 JTAG configuration signals . 91 2.11 Ethernet: Enhanced Three-Speed Ethernet (eTSEC) .40 3.11 Guidelines for high-speed interface termination . 93 2.12 USB 51 3.12 Thermal 94 2.13 Integrated flash controller .55 4 Package information . 96 2.14 Enhanced secure digital host controller (eSDHC) 59 4.1 Package parameters for P1014 96 2.15 Programmable Interrupt Controller (PIC) 4.2 Mechanical dimensions of P1014 WB-TePBGA . 96 specifications 61 5 Ordering information . 98 2.16 JTAG .62 5.1 Part marking 98 2 2.17 I C .64 6 Product documentation . 98 2.18 GPIO .66 7 Revision history . 99 2.19 TDM .68 2.20 High-Speed Serial Interfaces (HSSI) 70 P1014 QorIQ Integrated Processor Hardware Specifications, Rev. 4 2 Freescale Semiconductor