MPXN2020VMG116

Freescale Semiconductor Document Number: PXN20 Rev. 1, 09/2011 Data Sheet: Technical Data PXN20 PXN21 MAPBGA208 17 mm x 17 mm PXN20 Microcontroller Data Sheet PXN20 features: Internal conversion triggering for ADC Triggerable by internal timers or eMIOS200 32-bit CPU core complex (e200z650) Deserial Serial Peripheral Interface (DSPI) Compliant with Power Architecture embedded category Four individual DSPI modules 32 KB unified cache with line locking and eight-entry Full duplex, synchronous transfers store buffer16 Master or slave operation Execution speed static to 116 MHz 2 Inter-IC communication (I C) interface 32-bit I/O processor (e200z0) 2 Four individual I C modules Execution speed static to 1/2 CPU core speed (58 MHz) Multi-master operation 2 MB on-chip flash Serial Communication Interface (eSCI) module Supports read during program and erase operations, and Two-channel DMA interface multiple blocks allowing EEPROM emulation Configurable as LIN bus master 512 KB + 80 KB (592 KB) on-chip ECC SRAM (PXN20) eMIOS200 timed input/output 128 KB on-chip ECC SRAM (PXN21) 24 channels, 16-bit timers (PXN20) 16-entry Memory Protection Unit (PXN21 only) 32 channels, 16-bit timers (PXN21) Direct memory access controller Controller Area Network (FlexCAN) module 16-channel on PXN20 Compliant with CAN protocol specification, Version 32-channel on PXN21 2.0B active Fast ethernet controller 64 mailboxes, each configurable as transmit or receive Supports 10-Mbps and 100-Mbps IEEE 802.3 MII, Dual-channel FlexRay controller 10-Mbps 7-wire interface Full implementation of FlexRay Protocol Specification IEEE 802.3 MAC (compliant with IEEE 802.3 1998 2.1, RevA edition) 128 message buffers Media Local Bus (MLB) interface (PXN20 only) JTAG controller (PXN20 only) Supports 16 logical channels, max speed 1024 Fs Compliant with the IEEE 1149.1-2001 Interrupt controller (INTC) supports 316 external interrupt Nexus Development Interface (NDI) vectors (22 are reserved) Available in 256 MAPBGA package only System clocks Compliant with IEEE-ISTO 5001-2003 Frequency-modulated phase-locked loop (FMPLL) Nexus class 3 development support on e200z650 440MHz crystal oscillator (XTAL) Nexus class 2+ development support on e200z0 32 kHz crystal oscillator (XTAL) Internal voltage regulator allows operation from single Dedicated 16 MHz and 128 kHz internal RC oscillators 3.3 V or 5 V supply Analog to Digital Converter (ADC) module 10-bit A/D resolution 32 external channels 36 internal channels (PXN20) 64 internal channels (PXN21) Cross-Triggering Unit (PXN21 only) Freescale Semiconductor, Inc., 2011. All rights reserved.Table of Contents 1 Ordering information .3 4.6 Operating current specifications 32 1.1 Orderable parts 3 4.7 I/O pad current specifications . 34 1.2 PXN20 family feature set 3 4.8 Low voltage characteristics . 36 2 PXN20 block diagrams .5 4.9 Oscillators electrical characteristics . 36 3 Pin assignments 7 4.10 FMPLL electrical characteristics . 38 3.1 208-ball MAPBGA pin assignments 7 4.11 ADC electrical characteristics . 39 3.2 Pin muxing and reset states 8 4.12 Flash memory electrical characteristics . 39 4 Electrical characteristics .26 4.13 Pad AC specifications . 40 4.1 Maximum ratings 26 4.14 AC timing . 43 4.2 Thermal characteristics .27 5 Package characteristics . 58 4.3 ESD characteristics 30 5.1 Package mechanical data 58 4.4 VRC electrical specifications .30 6 Revision history . 60 4.5 DC electrical specifications 30 PXS30 Microcontroller Data Sheet, Rev. 1 2 Freescale Semiconductor