MPC875VR66

Document Number: MPC875EC Freescale Semiconductor Rev. 4, 08/2007 Technical Data MPC875/MPC870 PowerQUICC Hardware Specifications Contents This hardware specification contains detailed information on 1. Overview . 2 power considerations, DC/AC electrical characteristics, and 2. Features 2 AC timing specifications for the MPC875/MPC870. The 3. Maximum Tolerated Ratings . 9 CPU on the MPC875/MPC870 is a 32-bit core built on 4. Thermal Characteristics 10 5. Power Dissipation . 11 Power Architecture technology that incorporates memory 6. DC Characteristics 11 management units (MMUs) and instruction and data caches. 7. Thermal Calculation and Measurement 12 For functional characteristics of the MPC875/MPC870, refer 8. Power Supply and Power Sequencing . 14 9. Mandatory Reset Configurations . 15 to the MPC885 PowerQUICC Family Reference Manual. 10. Layout Practices 16 To locate published errata or updates for this document, refer 11. Bus Signal Timing 17 12. IEEE 1149.1 Electrical Specifications . 45 to the MPC875/MPC870 product summary page on our 13. CPM Electrical Characteristics . 47 website listed on the back cover of this document or, contact 14. USB Electrical Characteristics . 67 your local Freescale sales office. 15. FEC Electrical Characteristics . 67 16. Mechanical Data and Ordering Information . 71 17. Document Revision History . 80 Freescale Semiconductor, Inc., 20032007. All rights reserved.Overview 1Overview The MPC875/MPC870 is a versatile single-chip integrated microprocessor and peripheral combination that can be used in a variety of controller applications and communications and networking systems. The MPC875/MPC870 provides enhanced ATM functionality over that of other ATM-enabled members of the MPC860 family. Table 1 shows the functionality supported by the MPC875/MPC870. Table 1. MPC875/MPC870 Devices Cache (Kbytes) Ethernet Security Part SCC SMC USB Engine I Cache D Cache 10BaseT 10/100 MPC875 8812 1 1 1 Yes MPC870 8 8 2 1 1 No 2Features The MPC875/MPC870 is comprised of three modules that each use the 32-bit internal bus: a MPC8xx core, a system integration unit (SIU), and a communications processor module (CPM). The following list summarizes the key MPC875/MPC870 features: Embedded MPC8xx core up to 133 MHz Maximum frequency operation of the external bus is 80 MHz (in 1:1 mode) The 133-MHz core frequency supports 2:1 mode only The 66-/80-MHz core frequencies support both the 1:1 and 2:1 modes Single-issue, 32-bit core (compatible with the Power Architecture definition) with thirty-two 32-bit general-purpose registers (GPRs) The core performs branch prediction with conditional prefetch and without conditional execution 8-Kbyte data cache and 8-Kbyte instruction cache (see Table 1) Instruction cache is two-way, set-associative with 256 sets in 2 blocks Data cache is two-way, set-associative with 256 sets Cache coherency for both instruction and data caches is maintained on 128-bit (4-word) cache blocks Caches are physically addressed, implement a least recently used (LRU) replacement algorithm, and are lockable on a cache block basis MMUs with 32-entry TLB, fully associative instruction and data TLBs MMUs support multiple page sizes of 4, 16, and 512 Kbytes, and 8 Mbytes 16 virtual address spaces and 16 protection groups Advanced on-chip emulation debug mode Up to 32-bit data bus (dynamic bus sizing for 8, 16, and 32 bits) MPC875/MPC870 PowerQUICC Hardware Specifications, Rev. 4 2 Freescale Semiconductor