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MPC8323VRAFDCA

Product Image X-ON

Microprocessors - MPU PowerQUICC, 32 Bit Power Architecture SoC, 333MHz e300, QE, PCI, USB2.0, DDR1/2, UTOPIA, 0-105C
Manufacturer: NXP


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Manufacturer
NXP
Product Category
Microprocessors - MPU
RoHS - XON
Y Icon ROHS
Series
Mpc8323
Core
E300c2
Data Bus Width
32 bit
Maximum Clock Frequency
333 Mhz
Interface Type
Ethernet, I2c, Pcie, Spi, Uart, Usb
Operating Supply Voltage
1 V
Maximum Operating Temperature
+105 C
Mounting Style
Smd/Smt
Package / Case
PBGA-516
Memory Type
L1 Cache
Brand
Nxp / Freescale
I/O Voltage
1.8 v , 2.5 v , 3.3 v
L1 Cache Data Memory
16 Kb
L1 Cache Instruction Memory
16 Kb
Minimum Operating Temperature
0 C
Number Of Cores
1 Core
Number Of Timers/Counters
4 X 16 Bit
Processor Series
Powerquicc Ii Pro
Factory Pack Quantity :
40
Watchdog Timers
No Watchdog Timer
Cnhts
8542319000
Hts Code
8542310001
Mxhts
85423102
Taric
8542319000
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Document Number: MPC8323EEC Freescale Semiconductor Rev. 4, 09/2010 Technical Data MPC8323E PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications Contents This document provides an overview of the MPC8323E 1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 PowerQUICC II Pro processor features. The MPC8323E is a 2. Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . 6 cost-effective, highly integrated communications processor 3. Power Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 9 that addresses the requirements of several networking 4. Clock Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 10 5. RESET Initialization . . . . . . . . . . . . . . . . . . . . . . . . . 11 applications, including ADSL SOHO and residential 6. DDR1 and DDR2 SDRAM . . . . . . . . . . . . . . . . . . . . 13 gateways, modem/routers, industrial control, and test and 7. DUART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 measurement applications. The MPC8323E extends current 8. Ethernet and MII Management . . . . . . . . . . . . . . . . . 19 9. Local Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 PowerQUICC offerings, adding higher CPU performance, 10. JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 additional functionality, and faster interfaces, while 2 11. I C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 addressing the requirements related to time-to-market, price, 12. PCI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 power consumption, and board real estate. This document 13. Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 14. GPIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 describes the MPC8323E, and unless otherwise noted, the 15. IPIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 information also applies to the MPC8323, MPC8321E, and 16. SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 MPC8321. 17. TDM/SI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 18. UTOPIA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 To locate published errata or updates for this document, refer 19. HDLC, BISYNC, Transparent, and Synchronous to the MPC8323E product summary page on our website UART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 20. USB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 listed on the back cover of this document or contact your 21. Package and Pin Listings . . . . . . . . . . . . . . . . . . . . . 49 local Freescale sales office. 22. Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 23. Thermal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 24. System Design Information . . . . . . . . . . . . . . . . . . . 76 25. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . 79 26. Document Revision History . . . . . . . . . . . . . . . . . . . 80 ? 2010 Freescale Semiconductor, Inc. All rights reserved. Document Number: MPC8323EEC Freescale Semiconductor Rev. 4, 09/2010 Technical Data MPC8323E PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications Contents This document provides an overview of the MPC8323E 1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 PowerQUICC II Pro processor features. The MPC8323E is a 2. Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . 6 cost-effective, highly integrated communications processor 3. Power Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 9 that addresses the requirements of several networking 4. Clock Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 10 5. RESET Initialization . . . . . . . . . . . . . . . . . . . . . . . . . 11 applications, including ADSL SOHO and residential 6. DDR1 and DDR2 SDRAM . . . . . . . . . . . . . . . . . . . . 13 gateways, modem/routers, industrial control, and test and 7. DUART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 measurement applications. The MPC8323E extends current 8. Ethernet and MII Management . . . . . . . . . . . . . . . . . 19 9. Local Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 PowerQUICC offerings, adding higher CPU performance, 10. JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 additional functionality, and faster interfaces, while 2 11. I C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 addressing the requirements related to time-to-market, price, 12. PCI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 power consumption, and board real estate. This document 13. Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 14. GPIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 describes the MPC8323E, and unless otherwise noted, the 15. IPIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 information also applies to the MPC8323, MPC8321E, and 16. SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 MPC8321. 17. TDM/SI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 18. UTOPIA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 To locate published errata or updates for this document, refer 19. HDLC, BISYNC, Transparent, and Synchronous to the MPC8323E product summary page on our website UART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 20. USB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 listed on the back cover of this document or contact your 21. Package and Pin Listings . . . . . . . . . . . . . . . . . . . . . 49 local Freescale sales office. 22. Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 23. Thermal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 24. System Design Information . . . . . . . . . . . . . . . . . . . 76 25. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . 79 26. Document Revision History . . . . . . . . . . . . . . . . . . . 80 ? 2010 Freescale Semiconductor, Inc. All rights reserved. Overview 1Overview The MPC8323E incorporates the e300c2 (MPC603e-based) core built on Power Architecture? technology, which includes 16 Kbytes of L1 instruction and data caches, dual integer units, and on-chip memory management units (MMUs). The e300c2 core does not contain a floating point unit (FPU). The MPC8323E also includes a 32-bit PCI controller, four DMA channels, a security engine, and a 32-bit DDR1/DDR2 memory controller. A new communications complex based on QUICC Engine technology forms the heart of the networking capability of the MPC8323E. The QUICC Engine block contains several peripheral controllers and a 32-bit RISC controller. Protocol support is provided by the main workhorses of the device?the unified communication controllers (UCCs). Note that the MPC8321 and MPC8321E do not support UTOPIA. A block diagram of the MPC8323E is shown in Figure 1. MPC8323E e300c2 Core System Interface Unit (SIU) 16 KB 16 KB Security Engine (SEC 2.2) I-Cache D-Cache Memory Controllers Integer Unit Integer Unit GPCM/UPM (IU1) (IU2) DDR 32-Bit DDR1/DDR2 Interface Unit Classic G2 MMUs PCI PCI Controller Timers, Power Management, Local and JTAG/COP Local Bus QUICC Engine Block Bus Arbitration Multi-User DUART Accelerators RAM Baud Rate Serial DMA Generators and 2 I C 2 Virtual Single 32-Bit RISC CP DMAs Parallel I/O 4 Channel DMA Interrupt Controller Protection and Configuration Time Slot Assigner System Reset Serial Interface Clock Synthesizer 4 TDM Ports 3 MII/RMII 1 UL2/8-Bit Figure 1. MPC8323E Block Diagram Each of the five UCCs can support a variety of communication protocols: 10/100 Mbps Ethernet, serial ATM, HDLC, UART, and BISYNC?and, in the MPC8323E and MPC8323, multi-PHY ATM and ATM support for up to OC-3 speeds. MPC8323E PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 4 2 Freescale Semiconductor UCC1 UCC2 UCC3 UCC4 UCC5 SPI SPI USBDocument Number: MPC8323EEC Freescale Semiconductor Rev. 4, 09/2010 Technical Data MPC8323E PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications Contents This document provides an overview of the MPC8323E 1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 PowerQUICC II Pro processor features. The MPC8323E is a 2. Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . 6 cost-effective, highly integrated communications processor 3. Power Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 9 that addresses the requirements of several networking 4. Clock Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 10 5. RESET Initialization . . . . . . . . . . . . . . . . . . . . . . . . . 11 applications, including ADSL SOHO and residential 6. DDR1 and DDR2 SDRAM . . . . . . . . . . . . . . . . . . . . 13 gateways, modem/routers, industrial control, and test and 7. DUART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 measurement applications. The MPC8323E extends current 8. Ethernet and MII Management . . . . . . . . . . . . . . . . . 19 9. Local Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 PowerQUICC offerings, adding higher CPU performance, 10. JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 additional functionality, and faster interfaces, while 2 11. I C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 addressing the requirements related to time-to-market, price, 12. PCI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 power consumption, and board real estate. This document 13. Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 14. GPIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 describes the MPC8323E, and unless otherwise noted, the 15. IPIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 information also applies to the MPC8323, MPC8321E, and 16. SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 MPC8321. 17. TDM/SI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 18. UTOPIA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 To locate published errata or updates for this document, refer 19. HDLC, BISYNC, Transparent, and Synchronous to the MPC8323E product summary page on our website UART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 20. USB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 listed on the back cover of this document or contact your 21. Package and Pin Listings . . . . . . . . . . . . . . . . . . . . . 49 local Freescale sales office. 22. Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 23. Thermal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 24. System Design Information . . . . . . . . . . . . . . . . . . . 76 25. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . 79 26. Document Revision History . . . . . . . . . . . . . . . . . . . 80 ? 2010 Freescale Semiconductor, Inc. All rights reserved. Document Number: MPC8323EEC Freescale Semiconductor Rev. 4, 09/2010 Technical Data MPC8323E PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications Contents This document provides an overview of the MPC8323E 1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 PowerQUICC II Pro processor features. The MPC8323E is a 2. Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . 6 cost-effective, highly integrated communications processor 3. Power Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 9 that addresses the requirements of several networking 4. Clock Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 10 5. RESET Initialization . . . . . . . . . . . . . . . . . . . . . . . . . 11 applications, including ADSL SOHO and residential 6. DDR1 and DDR2 SDRAM . . . . . . . . . . . . . . . . . . . . 13 gateways, modem/routers, industrial control, and test and 7. DUART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 measurement applications. The MPC8323E extends current 8. Ethernet and MII Management . . . . . . . . . . . . . . . . . 19 9. Local Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 PowerQUICC offerings, adding higher CPU performance, 10. JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 additional functionality, and faster interfaces, while 2 11. I C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 addressing the requirements related to time-to-market, price, 12. PCI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 power consumption, and board real estate. This document 13. Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 14. GPIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 describes the MPC8323E, and unless otherwise noted, the 15. IPIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 information also applies to the MPC8323, MPC8321E, and 16. SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 MPC8321. 17. TDM/SI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 18. UTOPIA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 To locate published errata or updates for this document, refer 19. HDLC, BISYNC, Transparent, and Synchronous to the MPC8323E product summary page on our website UART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 20. USB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 listed on the back cover of this document or contact your 21. Package and Pin Listings . . . . . . . . . . . . . . . . . . . . . 49 local Freescale sales office. 22. Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 23. Thermal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 24. System Design Information . . . . . . . . . . . . . . . . . . . 76 25. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . 79 26. Document Revision History . . . . . . . . . . . . . . . . . . . 80 ? 2010 Freescale Semiconductor, Inc. All rights reserved. Overview 1Overview The MPC8323E incorporates the e300c2 (MPC603e-based) core built on Power Architecture? technology, which includes 16 Kbytes of L1 instruction and data caches, dual integer units, and on-chip memory management units (MMUs). The e300c2 core does not contain a floating point unit (FPU). The MPC8323E also includes a 32-bit PCI controller, four DMA channels, a security engine, and a 32-bit DDR1/DDR2 memory controller. A new communications complex based on QUICC Engine technology forms the heart of the networking capability of the MPC8323E. The QUICC Engine block contains several peripheral controllers and a 32-bit RISC controller. Protocol support is provided by the main workhorses of the device?the unified communication controllers (UCCs). Note that the MPC8321 and MPC8321E do not support UTOPIA. A block diagram of the MPC8323E is shown in Figure 1. MPC8323E e300c2 Core System Interface Unit (SIU) 16 KB 16 KB Security Engine (SEC 2.2) I-Cache D-Cache Memory Controllers Integer Unit Integer Unit GPCM/UPM (IU1) (IU2) DDR 32-Bit DDR1/DDR2 Interface Unit Classic G2 MMUs PCI PCI Controller Timers, Power Management, Local and JTAG/COP Local Bus QUICC Engine Block Bus Arbitration Multi-User DUART Accelerators RAM Baud Rate Serial DMA Generators and 2 I C 2 Virtual Single 32-Bit RISC CP DMAs Parallel I/O 4 Channel DMA Interrupt Controller Protection and Configuration Time Slot Assigner System Reset Serial Interface Clock Synthesizer 4 TDM Ports 3 MII/RMII 1 UL2/8-Bit Figure 1. MPC8323E Block Diagram Each of the five UCCs can support a variety of communication protocols: 10/100 Mbps Ethernet, serial ATM, HDLC, UART, and BISYNC?and, in the MPC8323E and MPC8323, multi-PHY ATM and ATM support for up to OC-3 speeds. MPC8323E PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 4 2 Freescale Semiconductor UCC1 UCC2 UCC3 UCC4 UCC5 SPI SPI USBOverview NOTE The QUICC Engine block can also support a UTOPIA level 2 capable of supporting 31 multi-PHY (MPC8323E- and MPC8323-specific). The MPC8323E security engine (SEC 2.2) allows CPU-intensive cryptographic operations to be offloaded from the main CPU core. The security-processing accelerator provides hardware acceleration for the DES, 3DES, AES, SHA-1, and MD-5 algorithms. In summary, the MPC8323E family provides users with a highly integrated, fully programmable communications processor. This helps ensure that a low-cost system solution can be quickly developed and offers flexibility to accommodate new standards and evolving system requirements. 1.1 MPC8323E Features Major features of the MPC8323E are as follows: ? High-performance, low-power, and cost-effective single-chip data-plane/control-plane solution for ATM or IP/Ethernet packet processing (or both). ? MPC8323E QUICC Engine block offers a future-proof solution for next generation designs by supporting programmable protocol termination and network interface termination to meet evolving protocol standards. ? Single platform architecture supports the convergence of IP packet networks and ATM networks. ? DDR1/DDR2 memory controller?one 32-bit interface at up to 266 MHz supporting both DDR1 and DDR2. ? An e300c2 core built on Power Architecture technology with 16-Kbyte instruction and data caches, and dual integer units. ? Peripheral interfaces such as 32-bit PCI (2.2) interface up to 66-MHz operation, 16-bit local bus interface up to 66-MHz operation, and USB 2.0 (full-/low-speed). ? Security engine provides acceleration for control and data plane security protocols. ? High degree of software compatibility with previous-generation PowerQUICC processor-based designs for backward compatibility and easier software migration. 1.1.1 Protocols The protocols are as follows: ? ATM SAR up to 155 Mbps (OC-3) full duplex, with ATM traffic shaping (ATF TM4.1) ? Support for ATM AAL1 structured and unstructured circuit emulation service (CES 2.0) ? Support for IMA and ATM transmission convergence sub-layer ? ATM OAM handling features compatible with ITU-T I.610 ? IP termination support for IPv4 and IPv6 packets including TOS, TTL, and header checksum processing ? Extensive support for ATM statistics and Ethernet RMON/MIB statistics ? Support for 64 channels of HDLC/transparent MPC8323E PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 4 Freescale Semiconductor 3 Document Number: MPC8323EEC Freescale Semiconductor Rev. 4, 09/2010 Technical Data MPC8323E PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications Contents This document provides an overview of the MPC8323E 1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 PowerQUICC II Pro processor features. The MPC8323E is a 2. Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . 6 cost-effective, highly integrated communications processor 3. Power Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 9 that addresses the requirements of several networking 4. Clock Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 10 5. RESET Initialization . . . . . . . . . . . . . . . . . . . . . . . . . 11 applications, including ADSL SOHO and residential 6. DDR1 and DDR2 SDRAM . . . . . . . . . . . . . . . . . . . . 13 gateways, modem/routers, industrial control, and test and 7. DUART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 measurement applications. The MPC8323E extends current 8. Ethernet and MII Management . . . . . . . . . . . . . . . . . 19 9. Local Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 PowerQUICC offerings, adding higher CPU performance, 10. JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 additional functionality, and faster interfaces, while 2 11. I C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 addressing the requirements related to time-to-market, price, 12. PCI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 power consumption, and board real estate. This document 13. Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 14. GPIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 describes the MPC8323E, and unless otherwise noted, the 15. IPIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 information also applies to the MPC8323, MPC8321E, and 16. SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 MPC8321. 17. TDM/SI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 18. UTOPIA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 To locate published errata or updates for this document, refer 19. HDLC, BISYNC, Transparent, and Synchronous to the MPC8323E product summary page on our website UART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 20. USB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 listed on the back cover of this document or contact your 21. Package and Pin Listings . . . . . . . . . . . . . . . . . . . . . 49 local Freescale sales office. 22. Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 23. Thermal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 24. System Design Information . . . . . . . . . . . . . . . . . . . 76 25. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . 79 26. Document Revision History . . . . . . . . . . . . . . . . . . . 80 ? 2010 Freescale Semiconductor, Inc. All rights reserved. Document Number: MPC8323EEC Freescale Semiconductor Rev. 4, 09/2010 Technical Data MPC8323E PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications Contents This document provides an overview of the MPC8323E 1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 PowerQUICC II Pro processor features. The MPC8323E is a 2. Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . 6 cost-effective, highly integrated communications processor 3. Power Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 9 that addresses the requirements of several networking 4. Clock Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 10 5. RESET Initialization . . . . . . . . . . . . . . . . . . . . . . . . . 11 applications, including ADSL SOHO and residential 6. DDR1 and DDR2 SDRAM . . . . . . . . . . . . . . . . . . . . 13 gateways, modem/routers, industrial control, and test and 7. DUART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 measurement applications. The MPC8323E extends current 8. Ethernet and MII Management . . . . . . . . . . . . . . . . . 19 9. Local Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 PowerQUICC offerings, adding higher CPU performance, 10. JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 additional functionality, and faster interfaces, while 2 11. I C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 addressing the requirements related to time-to-market, price, 12. PCI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 power consumption, and board real estate. This document 13. Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 14. GPIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 describes the MPC8323E, and unless otherwise noted, the 15. IPIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 information also applies to the MPC8323, MPC8321E, and 16. SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 MPC8321. 17. TDM/SI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 18. UTOPIA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 To locate published errata or updates for this document, refer 19. HDLC, BISYNC, Transparent, and Synchronous to the MPC8323E product summary page on our website UART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 20. USB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 listed on the back cover of this document or contact your 21. Package and Pin Listings . . . . . . . . . . . . . . . . . . . . . 49 local Freescale sales office. 22. Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 23. Thermal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 24. System Design Information . . . . . . . . . . . . . . . . . . . 76 25. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . 79 26. Document Revision History . . . . . . . . . . . . . . . . . . . 80 ? 2010 Freescale Semiconductor, Inc. All rights reserved. Overview 1Overview The MPC8323E incorporates the e300c2 (MPC603e-based) core built on Power Architecture? technology, which includes 16 Kbytes of L1 instruction and data caches, dual integer units, and on-chip memory management units (MMUs). The e300c2 core does not contain a floating point unit (FPU). The MPC8323E also includes a 32-bit PCI controller, four DMA channels, a security engine, and a 32-bit DDR1/DDR2 memory controller. A new communications complex based on QUICC Engine technology forms the heart of the networking capability of the MPC8323E. The QUICC Engine block contains several peripheral controllers and a 32-bit RISC controller. Protocol support is provided by the main workhorses of the device?the unified communication controllers (UCCs). Note that the MPC8321 and MPC8321E do not support UTOPIA. A block diagram of the MPC8323E is shown in Figure 1. MPC8323E e300c2 Core System Interface Unit (SIU) 16 KB 16 KB Security Engine (SEC 2.2) I-Cache D-Cache Memory Controllers Integer Unit Integer Unit GPCM/UPM (IU1) (IU2) DDR 32-Bit DDR1/DDR2 Interface Unit Classic G2 MMUs PCI PCI Controller Timers, Power Management, Local and JTAG/COP Local Bus QUICC Engine Block Bus Arbitration Multi-User DUART Accelerators RAM Baud Rate Serial DMA Generators and 2 I C 2 Virtual Single 32-Bit RISC CP DMAs Parallel I/O 4 Channel DMA Interrupt Controller Protection and Configuration Time Slot Assigner System Reset Serial Interface Clock Synthesizer 4 TDM Ports 3 MII/RMII 1 UL2/8-Bit Figure 1. MPC8323E Block Diagram Each of the five UCCs can support a variety of communication protocols: 10/100 Mbps Ethernet, serial ATM, HDLC, UART, and BISYNC?and, in the MPC8323E and MPC8323, multi-PHY ATM and ATM support for up to OC-3 speeds. MPC8323E PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 4 2 Freescale Semiconductor UCC1 UCC2 UCC3 UCC4 UCC5 SPI SPI USBDocument Number: MPC8323EEC Freescale Semiconductor Rev. 4, 09/2010 Technical Data MPC8323E PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications Contents This document provides an overview of the MPC8323E 1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 PowerQUICC II Pro processor features. The MPC8323E is a 2. Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . 6 cost-effective, highly integrated communications processor 3. Power Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 9 that addresses the requirements of several networking 4. Clock Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 10 5. RESET Initialization . . . . . . . . . . . . . . . . . . . . . . . . . 11 applications, including ADSL SOHO and residential 6. DDR1 and DDR2 SDRAM . . . . . . . . . . . . . . . . . . . . 13 gateways, modem/routers, industrial control, and test and 7. DUART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 measurement applications. The MPC8323E extends current 8. Ethernet and MII Management . . . . . . . . . . . . . . . . . 19 9. Local Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 PowerQUICC offerings, adding higher CPU performance, 10. JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 additional functionality, and faster interfaces, while 2 11. I C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 addressing the requirements related to time-to-market, price, 12. PCI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 power consumption, and board real estate. This document 13. Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 14. GPIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 describes the MPC8323E, and unless otherwise noted, the 15. IPIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 information also applies to the MPC8323, MPC8321E, and 16. SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 MPC8321. 17. TDM/SI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 18. UTOPIA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 To locate published errata or updates for this document, refer 19. HDLC, BISYNC, Transparent, and Synchronous to the MPC8323E product summary page on our website UART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 20. USB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 listed on the back cover of this document or contact your 21. Package and Pin Listings . . . . . . . . . . . . . . . . . . . . . 49 local Freescale sales office. 22. Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 23. Thermal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 24. System Design Information . . . . . . . . . . . . . . . . . . . 76 25. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . 79 26. Document Revision History . . . . . . . . . . . . . . . . . . . 80 ? 2010 Freescale Semiconductor, Inc. All rights reserved. Document Number: MPC8323EEC Freescale Semiconductor Rev. 4, 09/2010 Technical Data MPC8323E PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications Contents This document provides an overview of the MPC8323E 1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 PowerQUICC II Pro processor features. The MPC8323E is a 2. Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . 6 cost-effective, highly integrated communications processor 3. Power Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 9 that addresses the requirements of several networking 4. Clock Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 10 5. RESET Initialization . . . . . . . . . . . . . . . . . . . . . . . . . 11 applications, including ADSL SOHO and residential 6. DDR1 and DDR2 SDRAM . . . . . . . . . . . . . . . . . . . . 13 gateways, modem/routers, industrial control, and test and 7. DUART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 measurement applications. The MPC8323E extends current 8. Ethernet and MII Management . . . . . . . . . . . . . . . . . 19 9. Local Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 PowerQUICC offerings, adding higher CPU performance, 10. JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 additional functionality, and faster interfaces, while 2 11. I C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 addressing the requirements related to time-to-market, price, 12. PCI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 power consumption, and board real estate. This document 13. Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 14. GPIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 describes the MPC8323E, and unless otherwise noted, the 15. IPIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 information also applies to the MPC8323, MPC8321E, and 16. SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 MPC8321. 17. TDM/SI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 18. UTOPIA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 To locate published errata or updates for this document, refer 19. HDLC, BISYNC, Transparent, and Synchronous to the MPC8323E product summary page on our website UART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 20. USB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 listed on the back cover of this document or contact your 21. Package and Pin Listings . . . . . . . . . . . . . . . . . . . . . 49 local Freescale sales office. 22. Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 23. Thermal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 24. System Design Information . . . . . . . . . . . . . . . . . . . 76 25. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . 79 26. Document Revision History . . . . . . . . . . . . . . . . . . . 80 ? 2010 Freescale Semiconductor, Inc. All rights reserved. Overview 1Overview The MPC8323E incorporates the e300c2 (MPC603e-based) core built on Power Architecture? technology, which includes 16 Kbytes of L1 instruction and data caches, dual integer units, and on-chip memory management units (MMUs). The e300c2 core does not contain a floating point unit (FPU). The MPC8323E also includes a 32-bit PCI controller, four DMA channels, a security engine, and a 32-bit DDR1/DDR2 memory controller. A new communications complex based on QUICC Engine technology forms the heart of the networking capability of the MPC8323E. The QUICC Engine block contains several peripheral controllers and a 32-bit RISC controller. Protocol support is provided by the main workhorses of the device?the unified communication controllers (UCCs). Note that the MPC8321 and MPC8321E do not support UTOPIA. A block diagram of the MPC8323E is shown in Figure 1. MPC8323E e300c2 Core System Interface Unit (SIU) 16 KB 16 KB Security Engine (SEC 2.2) I-Cache D-Cache Memory Controllers Integer Unit Integer Unit GPCM/UPM (IU1) (IU2) DDR 32-Bit DDR1/DDR2 Interface Unit Classic G2 MMUs PCI PCI Controller Timers, Power Management, Local and JTAG/COP Local Bus QUICC Engine Block Bus Arbitration Multi-User DUART Accelerators RAM Baud Rate Serial DMA Generators and 2 I C 2 Virtual Single 32-Bit RISC CP DMAs Parallel I/O 4 Channel DMA Interrupt Controller Protection and Configuration Time Slot Assigner System Reset Serial Interface Clock Synthesizer 4 TDM Ports 3 MII/RMII 1 UL2/8-Bit Figure 1. MPC8323E Block Diagram Each of the five UCCs can support a variety of communication protocols: 10/100 Mbps Ethernet, serial ATM, HDLC, UART, and BISYNC?and, in the MPC8323E and MPC8323, multi-PHY ATM and ATM support for up to OC-3 speeds. MPC8323E PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 4 2 Freescale Semiconductor UCC1 UCC2 UCC3 UCC4 UCC5 SPI SPI USBOverview NOTE The QUICC Engine block can also support a UTOPIA level 2 capable of supporting 31 multi-PHY (MPC8323E- and MPC8323-specific). The MPC8323E security engine (SEC 2.2) allows CPU-intensive cryptographic operations to be offloaded from the main CPU core. The security-processing accelerator provides hardware acceleration for the DES, 3DES, AES, SHA-1, and MD-5 algorithms. In summary, the MPC8323E family provides users with a highly integrated, fully programmable communications processor. This helps ensure that a low-cost system solution can be quickly developed and offers flexibility to accommodate new standards and evolving system requirements. 1.1 MPC8323E Features Major features of the MPC8323E are as follows: ? High-performance, low-power, and cost-effective single-chip data-plane/control-plane solution for ATM or IP/Ethernet packet processing (or both). ? MPC8323E QUICC Engine block offers a future-proof solution for next generation designs by supporting programmable protocol termination and network interface termination to meet evolving protocol standards. ? Single platform architecture supports the convergence of IP packet networks and ATM networks. ? DDR1/DDR2 memory controller?one 32-bit interface at up to 266 MHz supporting both DDR1 and DDR2. ? An e300c2 core built on Power Architecture technology with 16-Kbyte instruction and data caches, and dual integer units. ? Peripheral interfaces such as 32-bit PCI (2.2) interface up to 66-MHz operation, 16-bit local bus interface up to 66-MHz operation, and USB 2.0 (full-/low-speed). ? Security engine provides acceleration for control and data plane security protocols. ? High degree of software compatibility with previous-generation PowerQUICC processor-based designs for backward compatibility and easier software migration. 1.1.1 Protocols The protocols are as follows: ? ATM SAR up to 155 Mbps (OC-3) full duplex, with ATM traffic shaping (ATF TM4.1) ? Support for ATM AAL1 structured and unstructured circuit emulation service (CES 2.0) ? Support for IMA and ATM transmission convergence sub-layer ? ATM OAM handling features compatible with ITU-T I.610 ? IP termination support for IPv4 and IPv6 packets including TOS, TTL, and header checksum processing ? Extensive support for ATM statistics and Ethernet RMON/MIB statistics ? Support for 64 channels of HDLC/transparent MPC8323E PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 4 Freescale Semiconductor 3

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