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Document Number: MPC8323EEC Freescale Semiconductor Rev. 4, 09/2010 Technical Data MPC8323E PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications Contents This document provides an overview of the MPC8323E 1. Overview . 2 PowerQUICC II Pro processor features. The MPC8323E is a 2. Electrical Characteristics 6 cost-effective, highly integrated communications processor 3. Power Characteristics . 9 that addresses the requirements of several networking 4. Clock Input Timing 10 5. RESET Initialization . 11 applications, including ADSL SOHO and residential 6. DDR1 and DDR2 SDRAM 13 gateways, modem/routers, industrial control, and test and 7. DUART . 19 measurement applications. The MPC8323E extends current 8. Ethernet and MII Management . 19 9. Local Bus . 26 PowerQUICC offerings, adding higher CPU performance, 10. JTAG . 29 additional functionality, and faster interfaces, while 2 11. I C . 33 addressing the requirements related to time-to-market, price, 12. PCI 35 power consumption, and board real estate. This document 13. Timers 37 14. GPIO . 38 describes the MPC8323E, and unless otherwise noted, the 15. IPIC 39 information also applies to the MPC8323, MPC8321E, and 16. SPI . 40 MPC8321. 17. TDM/SI . 41 18. UTOPIA 43 To locate published errata or updates for this document, refer 19. HDLC, BISYNC, Transparent, and Synchronous to the MPC8323E product summary page on our website UART .45 20. USB 48 listed on the back cover of this document or contact your 21. Package and Pin Listings . 49 local Freescale sales office. 22. Clocking 64 23. Thermal . 71 24. System Design Information . 76 25. Ordering Information 79 26. Document Revision History . 80 2010 Freescale Semiconductor, Inc. All rights reserved. Overview 1Overview The MPC8323E incorporates the e300c2 (MPC603e-based) core built on Power Architecture technology, which includes 16 Kbytes of L1 instruction and data caches, dual integer units, and on-chip memory management units (MMUs). The e300c2 core does not contain a floating point unit (FPU). The MPC8323E also includes a 32-bit PCI controller, four DMA channels, a security engine, and a 32-bit DDR1/DDR2 memory controller. A new communications complex based on QUICC Engine technology forms the heart of the networking capability of the MPC8323E. The QUICC Engine block contains several peripheral controllers and a 32-bit RISC controller. Protocol support is provided by the main workhorses of the devicethe unified communication controllers (UCCs). Note that the MPC8321 and MPC8321E do not support UTOPIA. A block diagram of the MPC8323E is shown in Figure 1. MPC8323E e300c2 Core System Interface Unit (SIU) 16 KB 16 KB Security Engine (SEC 2.2) I-Cache D-Cache Memory Controllers Integer Unit Integer Unit GPCM/UPM (IU1) (IU2) DDR 32-Bit DDR1/DDR2 Interface Unit Classic G2 MMUs PCI PCI Controller Timers, Power Management, Local and JTAG/COP Local Bus QUICC Engine Block Bus Arbitration Multi-User DUART Accelerators RAM Baud Rate Serial DMA Generators and 2 I C 2 Virtual Single 32-Bit RISC CP DMAs Parallel I/O 4 Channel DMA Interrupt Controller Protection and Configuration Time Slot Assigner System Reset Serial Interface Clock Synthesizer 4 TDM Ports 3 MII/RMII 1 UL2/8-Bit Figure 1. MPC8323E Block Diagram Each of the five UCCs can support a variety of communication protocols: 10/100 Mbps Ethernet, serial ATM, HDLC, UART, and BISYNCand, in the MPC8323E and MPC8323, multi-PHY ATM and ATM support for up to OC-3 speeds. MPC8323E PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 4 2 Freescale Semiconductor UCC1 UCC2 UCC3 UCC4 UCC5 SPI SPI USB