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MCZ33903DP3EK

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Power Management Specialized - PMIC System Basis Chip, 2x 3.3 V/400mA LDOs, 3 wakeup, SOIC 32
Manufacturer: NXP


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Manufacturer
NXP
Product Category
Power Management Specialised - PMIC
RoHS - XON
Y Icon ROHS
Series
Mc33903/4/5
Brand
NXP
Product Type
Power Management Specialized - Pmic
Factory Pack Quantity :
42
Subcategory
Pmic - Power Management Ics
Tradename
Smartmos
Cnhts
8542390000
Hts Code
8542390001
Mxhts
85423901
Taric
8542399000
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NXP Semiconductors Document Number: MC33903_4_5 Rev. 14.0, 2/2018 Data Sheet: Advance Information SBC Gen2 with CAN high speed and 33903/ 33903/4/5 LIN interface The 33903/4/5 is the second generation family of the System Basis Chip (SBC). It combines several features and enhances present module designs. The device works as an advanced power management unit for the MCU with additional SYSTEM BASIS CHIP integrated circuits such as sensors and CAN transceivers. It has a built-in enhanced high-speed CAN interface (ISO11898-2 and -5) with local and bus failure diagnostics, protection, and fail-safe operation modes. The SBC may include zero, one or two LIN 2.1 interfaces with LIN output pin switches. It includes up to four wake-up input pins that can also be configured as output drivers for flexibility. This device is powered by SMARTMOS technology. This device implements multiple Low-power (LP) modes, with very low-current consumption. In addition, the device is part of a family concept where pin compatibility adds versatility to module design. EK Suffix (Pb-free) EK Suffix (Pb-free) 98ASA10556D 98ASA10506D The 33903/4/5 also implements an innovative and advanced fail-safe state 32-PIN SOIC 54-PIN SOIC machine and concept solution. Applications Features ? Voltage regulator for MCU, 5.0 or 3.3 V, part number selectable, with ? Aircraft and marine systems possibility of usage external PNP to extend current capability and share power ? Automotive and robotic systems dissipation ? Farm equipment ? Voltage, current, and temperature protection ? Industrial actuator controls ? Extremely low quiescent current in LP modes ? Lamp and inductive load controls ? Fully-protected embedded 5.0 V regulator for the CAN driver ? DC motor control applications requiring diagnostics ? Multiple undervoltage detections to address various MCU specifications and ? Applications where high-side switch control is system operation modes (i.e. cranking) required ? Auxiliary 5.0 or 3.3 V SPI configurable regulator, for additional ICs, with overcurrent detection and undervoltage protection ? MUX output pin for device internal analog signal monitoring and power supply monitoring ? Advanced SPI, MCU, ECU power supply, and critical pins diagnostics and monitoring. ? Multiple wake-up sources in LP modes: CAN or LIN bus, I/O transition, automatic timer, SPI message, and V overcurrent detection. DD ? ISO11898-5 high-speed CAN interface compatibility for baud rates of 40 kb/s to 1.0 Mb/s ? Scalable product family of devices ranging from 0 to 2 LINs which are compatible to J2602-2 and LIN 2.1 * This document contains certain information on a new product. Specifications and information herein are subject to change without notice. ? NXP B.V. 2018.NXP Semiconductors Document Number: MC33903_4_5 Rev. 14.0, 2/2018 Data Sheet: Advance Information SBC Gen2 with CAN high speed and 33903/ 33903/4/5 LIN interface The 33903/4/5 is the second generation family of the System Basis Chip (SBC). It combines several features and enhances present module designs. The device works as an advanced power management unit for the MCU with additional SYSTEM BASIS CHIP integrated circuits such as sensors and CAN transceivers. It has a built-in enhanced high-speed CAN interface (ISO11898-2 and -5) with local and bus failure diagnostics, protection, and fail-safe operation modes. The SBC may include zero, one or two LIN 2.1 interfaces with LIN output pin switches. It includes up to four wake-up input pins that can also be configured as output drivers for flexibility. This device is powered by SMARTMOS technology. This device implements multiple Low-power (LP) modes, with very low-current consumption. In addition, the device is part of a family concept where pin compatibility adds versatility to module design. EK Suffix (Pb-free) EK Suffix (Pb-free) 98ASA10556D 98ASA10506D The 33903/4/5 also implements an innovative and advanced fail-safe state 32-PIN SOIC 54-PIN SOIC machine and concept solution. Applications Features ? Voltage regulator for MCU, 5.0 or 3.3 V, part number selectable, with ? Aircraft and marine systems possibility of usage external PNP to extend current capability and share power ? Automotive and robotic systems dissipation ? Farm equipment ? Voltage, current, and temperature protection ? Industrial actuator controls ? Extremely low quiescent current in LP modes ? Lamp and inductive load controls ? Fully-protected embedded 5.0 V regulator for the CAN driver ? DC motor control applications requiring diagnostics ? Multiple undervoltage detections to address various MCU specifications and ? Applications where high-side switch control is system operation modes (i.e. cranking) required ? Auxiliary 5.0 or 3.3 V SPI configurable regulator, for additional ICs, with overcurrent detection and undervoltage protection ? MUX output pin for device internal analog signal monitoring and power supply monitoring ? Advanced SPI, MCU, ECU power supply, and critical pins diagnostics and monitoring. ? Multiple wake-up sources in LP modes: CAN or LIN bus, I/O transition, automatic timer, SPI message, and V overcurrent detection. DD ? ISO11898-5 high-speed CAN interface compatibility for baud rates of 40 kb/s to 1.0 Mb/s ? Scalable product family of devices ranging from 0 to 2 LINs which are compatible to J2602-2 and LIN 2.1 * This document contains certain information on a new product. Specifications and information herein are subject to change without notice. ? NXP B.V. 2018.Table of Contents 1. Simplified application diagrams ..................................................................................................................................................... 3 2. Orderable part ................................................................................................................................................................................ 7 3. Internal block diagrams .................................................................................................................................................................. 9 4. Pin Connections ........................................................................................................................................................................... 11 4.1. Pinout diagram ....................................................................................................................................................................... 11 5. Electrical characteristics .............................................................................................................................................................. 16 5.1. Maximum ratings .................................................................................................................................................................... 16 5.2. Static electrical characteristics ............................................................................................................................................... 18 5.3. Dynamic electrical characteristics .......................................................................................................................................... 26 5.4. Timing diagrams .................................................................................................................................................................... 29 6. Functional description .................................................................................................................................................................. 32 6.1. Introduction ............................................................................................................................................................................ 32 6.2. Functional pin description ...................................................................................................................................................... 32 7. Functional device operation ......................................................................................................................................................... 36 7.1. Mode and state description .................................................................................................................................................... 36 7.2. LP modes ............................................................................................................................................................................... 37 7.3. State diagram ......................................................................................................................................................................... 39 7.4. Mode change ......................................................................................................................................................................... 40 7.5. Watchdog operation ............................................................................................................................................................... 40 7.6. Functional block operation versus mode ............................................................................................................................... 43 7.7. Illustration of device mode transitions .................................................................................................................................... 44 7.8. Cyclic sense operation during LP modes ............................................................................................................................... 45 7.9. Cyclic INT operation during LP VDD on mode ....................................................................................................................... 47 7.10. Behavior at power up and power down ................................................................................................................................ 48 7.11. Fail-safe operation ............................................................................................................................................................... 51 8. CAN interface .............................................................................................................................................................................. 55 8.1. CAN interface description ...................................................................................................................................................... 55 8.2. CAN bus fault diagnostic ........................................................................................................................................................ 58 9. LIN block ...................................................................................................................................................................................... 62 9.1. LIN interface description ........................................................................................................................................................ 62 9.2. LIN operational modes ........................................................................................................................................................... 63 10. Serial peripheral interface .......................................................................................................................................................... 64 10.1. High level overview .............................................................................................................................................................. 64 10.2. Detail operation .................................................................................................................................................................... 64 10.3. Detail of control bits and register mapping ........................................................................................................................... 68 10.4. Flags and device status ....................................................................................................................................................... 84 11. Typical applications ................................................................................................................................................................... 92 12. Packaging ................................................................................................................................................................................ 100 12.1. SOIC 32 package dimensions ........................................................................................................................................... 100 12.2. SOIC 54 package dimensions ........................................................................................................................................... 103 13. Revision history ....................................................................................................................................................................... 106 33903/4/5 2 NXP SemiconductorsNXP Semiconductors Document Number: MC33903_4_5 Rev. 14.0, 2/2018 Data Sheet: Advance Information SBC Gen2 with CAN high speed and 33903/ 33903/4/5 LIN interface The 33903/4/5 is the second generation family of the System Basis Chip (SBC). It combines several features and enhances present module designs. The device works as an advanced power management unit for the MCU with additional SYSTEM BASIS CHIP integrated circuits such as sensors and CAN transceivers. It has a built-in enhanced high-speed CAN interface (ISO11898-2 and -5) with local and bus failure diagnostics, protection, and fail-safe operation modes. The SBC may include zero, one or two LIN 2.1 interfaces with LIN output pin switches. It includes up to four wake-up input pins that can also be configured as output drivers for flexibility. This device is powered by SMARTMOS technology. This device implements multiple Low-power (LP) modes, with very low-current consumption. In addition, the device is part of a family concept where pin compatibility adds versatility to module design. EK Suffix (Pb-free) EK Suffix (Pb-free) 98ASA10556D 98ASA10506D The 33903/4/5 also implements an innovative and advanced fail-safe state 32-PIN SOIC 54-PIN SOIC machine and concept solution. Applications Features ? Voltage regulator for MCU, 5.0 or 3.3 V, part number selectable, with ? Aircraft and marine systems possibility of usage external PNP to extend current capability and share power ? Automotive and robotic systems dissipation ? Farm equipment ? Voltage, current, and temperature protection ? Industrial actuator controls ? Extremely low quiescent current in LP modes ? Lamp and inductive load controls ? Fully-protected embedded 5.0 V regulator for the CAN driver ? DC motor control applications requiring diagnostics ? Multiple undervoltage detections to address various MCU specifications and ? Applications where high-side switch control is system operation modes (i.e. cranking) required ? Auxiliary 5.0 or 3.3 V SPI configurable regulator, for additional ICs, with overcurrent detection and undervoltage protection ? MUX output pin for device internal analog signal monitoring and power supply monitoring ? Advanced SPI, MCU, ECU power supply, and critical pins diagnostics and monitoring. ? Multiple wake-up sources in LP modes: CAN or LIN bus, I/O transition, automatic timer, SPI message, and V overcurrent detection. DD ? ISO11898-5 high-speed CAN interface compatibility for baud rates of 40 kb/s to 1.0 Mb/s ? Scalable product family of devices ranging from 0 to 2 LINs which are compatible to J2602-2 and LIN 2.1 * This document contains certain information on a new product. Specifications and information herein are subject to change without notice. ? NXP B.V. 2018.NXP Semiconductors Document Number: MC33903_4_5 Rev. 14.0, 2/2018 Data Sheet: Advance Information SBC Gen2 with CAN high speed and 33903/ 33903/4/5 LIN interface The 33903/4/5 is the second generation family of the System Basis Chip (SBC). It combines several features and enhances present module designs. The device works as an advanced power management unit for the MCU with additional SYSTEM BASIS CHIP integrated circuits such as sensors and CAN transceivers. It has a built-in enhanced high-speed CAN interface (ISO11898-2 and -5) with local and bus failure diagnostics, protection, and fail-safe operation modes. The SBC may include zero, one or two LIN 2.1 interfaces with LIN output pin switches. It includes up to four wake-up input pins that can also be configured as output drivers for flexibility. This device is powered by SMARTMOS technology. This device implements multiple Low-power (LP) modes, with very low-current consumption. In addition, the device is part of a family concept where pin compatibility adds versatility to module design. EK Suffix (Pb-free) EK Suffix (Pb-free) 98ASA10556D 98ASA10506D The 33903/4/5 also implements an innovative and advanced fail-safe state 32-PIN SOIC 54-PIN SOIC machine and concept solution. Applications Features ? Voltage regulator for MCU, 5.0 or 3.3 V, part number selectable, with ? Aircraft and marine systems possibility of usage external PNP to extend current capability and share power ? Automotive and robotic systems dissipation ? Farm equipment ? Voltage, current, and temperature protection ? Industrial actuator controls ? Extremely low quiescent current in LP modes ? Lamp and inductive load controls ? Fully-protected embedded 5.0 V regulator for the CAN driver ? DC motor control applications requiring diagnostics ? Multiple undervoltage detections to address various MCU specifications and ? Applications where high-side switch control is system operation modes (i.e. cranking) required ? Auxiliary 5.0 or 3.3 V SPI configurable regulator, for additional ICs, with overcurrent detection and undervoltage protection ? MUX output pin for device internal analog signal monitoring and power supply monitoring ? Advanced SPI, MCU, ECU power supply, and critical pins diagnostics and monitoring. ? Multiple wake-up sources in LP modes: CAN or LIN bus, I/O transition, automatic timer, SPI message, and V overcurrent detection. DD ? ISO11898-5 high-speed CAN interface compatibility for baud rates of 40 kb/s to 1.0 Mb/s ? Scalable product family of devices ranging from 0 to 2 LINs which are compatible to J2602-2 and LIN 2.1 * This document contains certain information on a new product. Specifications and information herein are subject to change without notice. ? NXP B.V. 2018.Table of Contents 1. Simplified application diagrams ..................................................................................................................................................... 3 2. Orderable part ................................................................................................................................................................................ 7 3. Internal block diagrams .................................................................................................................................................................. 9 4. Pin Connections ........................................................................................................................................................................... 11 4.1. Pinout diagram ....................................................................................................................................................................... 11 5. Electrical characteristics .............................................................................................................................................................. 16 5.1. Maximum ratings .................................................................................................................................................................... 16 5.2. Static electrical characteristics ............................................................................................................................................... 18 5.3. Dynamic electrical characteristics .......................................................................................................................................... 26 5.4. Timing diagrams .................................................................................................................................................................... 29 6. Functional description .................................................................................................................................................................. 32 6.1. Introduction ............................................................................................................................................................................ 32 6.2. Functional pin description ...................................................................................................................................................... 32 7. Functional device operation ......................................................................................................................................................... 36 7.1. Mode and state description .................................................................................................................................................... 36 7.2. LP modes ............................................................................................................................................................................... 37 7.3. State diagram ......................................................................................................................................................................... 39 7.4. Mode change ......................................................................................................................................................................... 40 7.5. Watchdog operation ............................................................................................................................................................... 40 7.6. Functional block operation versus mode ............................................................................................................................... 43 7.7. Illustration of device mode transitions .................................................................................................................................... 44 7.8. Cyclic sense operation during LP modes ............................................................................................................................... 45 7.9. Cyclic INT operation during LP VDD on mode ....................................................................................................................... 47 7.10. Behavior at power up and power down ................................................................................................................................ 48 7.11. Fail-safe operation ............................................................................................................................................................... 51 8. CAN interface .............................................................................................................................................................................. 55 8.1. CAN interface description ...................................................................................................................................................... 55 8.2. CAN bus fault diagnostic ........................................................................................................................................................ 58 9. LIN block ...................................................................................................................................................................................... 62 9.1. LIN interface description ........................................................................................................................................................ 62 9.2. LIN operational modes ........................................................................................................................................................... 63 10. Serial peripheral interface .......................................................................................................................................................... 64 10.1. High level overview .............................................................................................................................................................. 64 10.2. Detail operation .................................................................................................................................................................... 64 10.3. Detail of control bits and register mapping ........................................................................................................................... 68 10.4. Flags and device status ....................................................................................................................................................... 84 11. Typical applications ................................................................................................................................................................... 92 12. Packaging ................................................................................................................................................................................ 100 12.1. SOIC 32 package dimensions ........................................................................................................................................... 100 12.2. SOIC 54 package dimensions ........................................................................................................................................... 103 13. Revision history ....................................................................................................................................................................... 106 33903/4/5 2 NXP SemiconductorsSIMPLIFIED APPLICATION DIAGRAMS 1 Simplified application diagrams * = Optional 33905D V BAT (5.0 V/3.3 V) D1 Q2 Q1* VBAUX VCAUX VSUP1 VAUX VE VB V VDD DD VSUP2 RST SAFE DBG INT GND MOSI VSENSE SCLK SPI MCU MISO I/O-0 CS A/D MUX-OUT I/O-1 5V-CAN CANH TXD SPLIT RXD CAN Bus CANL TXD-L1 LIN-TERM 1 RXD-L1 LIN Bus LIN-1 TXD-L2 LIN- TERM 2 RXD-L2 LIN Bus LIN-2 Figure 1. 33905D simplified application diagram * = Optional 33905S V BAT (5.0 V/3.3 V) D1 Q2 Q1* VBAUX VCAUX VSUP1 VAUX VE VB V VDD DD VSUP2 SAFE RST DBG INT GND MOSI VSENSE SCLK SPI MCU MISO I/O-0 CS A/D MUX-OUT I/O-1 5V-CAN CANH TXD SPLIT RXD CAN Bus CANL TXD-L V BAT LIN-T RXD-L LIN Bus LIN I/O-3 Figure 2. 33905S simplified application diagram 33903/4/5 NXP Semiconductors 3NXP Semiconductors Document Number: MC33903_4_5 Rev. 14.0, 2/2018 Data Sheet: Advance Information SBC Gen2 with CAN high speed and 33903/ 33903/4/5 LIN interface The 33903/4/5 is the second generation family of the System Basis Chip (SBC). It combines several features and enhances present module designs. The device works as an advanced power management unit for the MCU with additional SYSTEM BASIS CHIP integrated circuits such as sensors and CAN transceivers. It has a built-in enhanced high-speed CAN interface (ISO11898-2 and -5) with local and bus failure diagnostics, protection, and fail-safe operation modes. The SBC may include zero, one or two LIN 2.1 interfaces with LIN output pin switches. It includes up to four wake-up input pins that can also be configured as output drivers for flexibility. This device is powered by SMARTMOS technology. This device implements multiple Low-power (LP) modes, with very low-current consumption. In addition, the device is part of a family concept where pin compatibility adds versatility to module design. EK Suffix (Pb-free) EK Suffix (Pb-free) 98ASA10556D 98ASA10506D The 33903/4/5 also implements an innovative and advanced fail-safe state 32-PIN SOIC 54-PIN SOIC machine and concept solution. Applications Features ? Voltage regulator for MCU, 5.0 or 3.3 V, part number selectable, with ? Aircraft and marine systems possibility of usage external PNP to extend current capability and share power ? Automotive and robotic systems dissipation ? Farm equipment ? Voltage, current, and temperature protection ? Industrial actuator controls ? Extremely low quiescent current in LP modes ? Lamp and inductive load controls ? Fully-protected embedded 5.0 V regulator for the CAN driver ? DC motor control applications requiring diagnostics ? Multiple undervoltage detections to address various MCU specifications and ? Applications where high-side switch control is system operation modes (i.e. cranking) required ? Auxiliary 5.0 or 3.3 V SPI configurable regulator, for additional ICs, with overcurrent detection and undervoltage protection ? MUX output pin for device internal analog signal monitoring and power supply monitoring ? Advanced SPI, MCU, ECU power supply, and critical pins diagnostics and monitoring. ? Multiple wake-up sources in LP modes: CAN or LIN bus, I/O transition, automatic timer, SPI message, and V overcurrent detection. DD ? ISO11898-5 high-speed CAN interface compatibility for baud rates of 40 kb/s to 1.0 Mb/s ? Scalable product family of devices ranging from 0 to 2 LINs which are compatible to J2602-2 and LIN 2.1 * This document contains certain information on a new product. Specifications and information herein are subject to change without notice. ? NXP B.V. 2018.NXP Semiconductors Document Number: MC33903_4_5 Rev. 14.0, 2/2018 Data Sheet: Advance Information SBC Gen2 with CAN high speed and 33903/ 33903/4/5 LIN interface The 33903/4/5 is the second generation family of the System Basis Chip (SBC). It combines several features and enhances present module designs. The device works as an advanced power management unit for the MCU with additional SYSTEM BASIS CHIP integrated circuits such as sensors and CAN transceivers. It has a built-in enhanced high-speed CAN interface (ISO11898-2 and -5) with local and bus failure diagnostics, protection, and fail-safe operation modes. The SBC may include zero, one or two LIN 2.1 interfaces with LIN output pin switches. It includes up to four wake-up input pins that can also be configured as output drivers for flexibility. This device is powered by SMARTMOS technology. This device implements multiple Low-power (LP) modes, with very low-current consumption. In addition, the device is part of a family concept where pin compatibility adds versatility to module design. EK Suffix (Pb-free) EK Suffix (Pb-free) 98ASA10556D 98ASA10506D The 33903/4/5 also implements an innovative and advanced fail-safe state 32-PIN SOIC 54-PIN SOIC machine and concept solution. Applications Features ? Voltage regulator for MCU, 5.0 or 3.3 V, part number selectable, with ? Aircraft and marine systems possibility of usage external PNP to extend current capability and share power ? Automotive and robotic systems dissipation ? Farm equipment ? Voltage, current, and temperature protection ? Industrial actuator controls ? Extremely low quiescent current in LP modes ? Lamp and inductive load controls ? Fully-protected embedded 5.0 V regulator for the CAN driver ? DC motor control applications requiring diagnostics ? Multiple undervoltage detections to address various MCU specifications and ? Applications where high-side switch control is system operation modes (i.e. cranking) required ? Auxiliary 5.0 or 3.3 V SPI configurable regulator, for additional ICs, with overcurrent detection and undervoltage protection ? MUX output pin for device internal analog signal monitoring and power supply monitoring ? Advanced SPI, MCU, ECU power supply, and critical pins diagnostics and monitoring. ? Multiple wake-up sources in LP modes: CAN or LIN bus, I/O transition, automatic timer, SPI message, and V overcurrent detection. DD ? ISO11898-5 high-speed CAN interface compatibility for baud rates of 40 kb/s to 1.0 Mb/s ? Scalable product family of devices ranging from 0 to 2 LINs which are compatible to J2602-2 and LIN 2.1 * This document contains certain information on a new product. Specifications and information herein are subject to change without notice. ? NXP B.V. 2018.Table of Contents 1. Simplified application diagrams ..................................................................................................................................................... 3 2. Orderable part ................................................................................................................................................................................ 7 3. Internal block diagrams .................................................................................................................................................................. 9 4. Pin Connections ........................................................................................................................................................................... 11 4.1. Pinout diagram ....................................................................................................................................................................... 11 5. Electrical characteristics .............................................................................................................................................................. 16 5.1. Maximum ratings .................................................................................................................................................................... 16 5.2. Static electrical characteristics ............................................................................................................................................... 18 5.3. Dynamic electrical characteristics .......................................................................................................................................... 26 5.4. Timing diagrams .................................................................................................................................................................... 29 6. Functional description .................................................................................................................................................................. 32 6.1. Introduction ............................................................................................................................................................................ 32 6.2. Functional pin description ...................................................................................................................................................... 32 7. Functional device operation ......................................................................................................................................................... 36 7.1. Mode and state description .................................................................................................................................................... 36 7.2. LP modes ............................................................................................................................................................................... 37 7.3. State diagram ......................................................................................................................................................................... 39 7.4. Mode change ......................................................................................................................................................................... 40 7.5. Watchdog operation ............................................................................................................................................................... 40 7.6. Functional block operation versus mode ............................................................................................................................... 43 7.7. Illustration of device mode transitions .................................................................................................................................... 44 7.8. Cyclic sense operation during LP modes ............................................................................................................................... 45 7.9. Cyclic INT operation during LP VDD on mode ....................................................................................................................... 47 7.10. Behavior at power up and power down ................................................................................................................................ 48 7.11. Fail-safe operation ............................................................................................................................................................... 51 8. CAN interface .............................................................................................................................................................................. 55 8.1. CAN interface description ...................................................................................................................................................... 55 8.2. CAN bus fault diagnostic ........................................................................................................................................................ 58 9. LIN block ...................................................................................................................................................................................... 62 9.1. LIN interface description ........................................................................................................................................................ 62 9.2. LIN operational modes ........................................................................................................................................................... 63 10. Serial peripheral interface .......................................................................................................................................................... 64 10.1. High level overview .............................................................................................................................................................. 64 10.2. Detail operation .................................................................................................................................................................... 64 10.3. Detail of control bits and register mapping ........................................................................................................................... 68 10.4. Flags and device status ....................................................................................................................................................... 84 11. Typical applications ................................................................................................................................................................... 92 12. Packaging ................................................................................................................................................................................ 100 12.1. SOIC 32 package dimensions ........................................................................................................................................... 100 12.2. SOIC 54 package dimensions ........................................................................................................................................... 103 13. Revision history ....................................................................................................................................................................... 106 33903/4/5 2 NXP SemiconductorsNXP Semiconductors Document Number: MC33903_4_5 Rev. 14.0, 2/2018 Data Sheet: Advance Information SBC Gen2 with CAN high speed and 33903/ 33903/4/5 LIN interface The 33903/4/5 is the second generation family of the System Basis Chip (SBC). It combines several features and enhances present module designs. The device works as an advanced power management unit for the MCU with additional SYSTEM BASIS CHIP integrated circuits such as sensors and CAN transceivers. It has a built-in enhanced high-speed CAN interface (ISO11898-2 and -5) with local and bus failure diagnostics, protection, and fail-safe operation modes. The SBC may include zero, one or two LIN 2.1 interfaces with LIN output pin switches. It includes up to four wake-up input pins that can also be configured as output drivers for flexibility. This device is powered by SMARTMOS technology. This device implements multiple Low-power (LP) modes, with very low-current consumption. In addition, the device is part of a family concept where pin compatibility adds versatility to module design. EK Suffix (Pb-free) EK Suffix (Pb-free) 98ASA10556D 98ASA10506D The 33903/4/5 also implements an innovative and advanced fail-safe state 32-PIN SOIC 54-PIN SOIC machine and concept solution. Applications Features ? Voltage regulator for MCU, 5.0 or 3.3 V, part number selectable, with ? Aircraft and marine systems possibility of usage external PNP to extend current capability and share power ? Automotive and robotic systems dissipation ? Farm equipment ? Voltage, current, and temperature protection ? Industrial actuator controls ? Extremely low quiescent current in LP modes ? Lamp and inductive load controls ? Fully-protected embedded 5.0 V regulator for the CAN driver ? DC motor control applications requiring diagnostics ? Multiple undervoltage detections to address various MCU specifications and ? Applications where high-side switch control is system operation modes (i.e. cranking) required ? Auxiliary 5.0 or 3.3 V SPI configurable regulator, for additional ICs, with overcurrent detection and undervoltage protection ? MUX output pin for device internal analog signal monitoring and power supply monitoring ? Advanced SPI, MCU, ECU power supply, and critical pins diagnostics and monitoring. ? Multiple wake-up sources in LP modes: CAN or LIN bus, I/O transition, automatic timer, SPI message, and V overcurrent detection. DD ? ISO11898-5 high-speed CAN interface compatibility for baud rates of 40 kb/s to 1.0 Mb/s ? Scalable product family of devices ranging from 0 to 2 LINs which are compatible to J2602-2 and LIN 2.1 * This document contains certain information on a new product. Specifications and information herein are subject to change without notice. ? NXP B.V. 2018.NXP Semiconductors Document Number: MC33903_4_5 Rev. 14.0, 2/2018 Data Sheet: Advance Information SBC Gen2 with CAN high speed and 33903/ 33903/4/5 LIN interface The 33903/4/5 is the second generation family of the System Basis Chip (SBC). It combines several features and enhances present module designs. The device works as an advanced power management unit for the MCU with additional SYSTEM BASIS CHIP integrated circuits such as sensors and CAN transceivers. It has a built-in enhanced high-speed CAN interface (ISO11898-2 and -5) with local and bus failure diagnostics, protection, and fail-safe operation modes. The SBC may include zero, one or two LIN 2.1 interfaces with LIN output pin switches. It includes up to four wake-up input pins that can also be configured as output drivers for flexibility. This device is powered by SMARTMOS technology. This device implements multiple Low-power (LP) modes, with very low-current consumption. In addition, the device is part of a family concept where pin compatibility adds versatility to module design. EK Suffix (Pb-free) EK Suffix (Pb-free) 98ASA10556D 98ASA10506D The 33903/4/5 also implements an innovative and advanced fail-safe state 32-PIN SOIC 54-PIN SOIC machine and concept solution. Applications Features ? Voltage regulator for MCU, 5.0 or 3.3 V, part number selectable, with ? Aircraft and marine systems possibility of usage external PNP to extend current capability and share power ? Automotive and robotic systems dissipation ? Farm equipment ? Voltage, current, and temperature protection ? Industrial actuator controls ? Extremely low quiescent current in LP modes ? Lamp and inductive load controls ? Fully-protected embedded 5.0 V regulator for the CAN driver ? DC motor control applications requiring diagnostics ? Multiple undervoltage detections to address various MCU specifications and ? Applications where high-side switch control is system operation modes (i.e. cranking) required ? Auxiliary 5.0 or 3.3 V SPI configurable regulator, for additional ICs, with overcurrent detection and undervoltage protection ? MUX output pin for device internal analog signal monitoring and power supply monitoring ? Advanced SPI, MCU, ECU power supply, and critical pins diagnostics and monitoring. ? Multiple wake-up sources in LP modes: CAN or LIN bus, I/O transition, automatic timer, SPI message, and V overcurrent detection. DD ? ISO11898-5 high-speed CAN interface compatibility for baud rates of 40 kb/s to 1.0 Mb/s ? Scalable product family of devices ranging from 0 to 2 LINs which are compatible to J2602-2 and LIN 2.1 * This document contains certain information on a new product. Specifications and information herein are subject to change without notice. ? NXP B.V. 2018.Table of Contents 1. Simplified application diagrams ..................................................................................................................................................... 3 2. Orderable part ................................................................................................................................................................................ 7 3. Internal block diagrams .................................................................................................................................................................. 9 4. Pin Connections ........................................................................................................................................................................... 11 4.1. Pinout diagram ....................................................................................................................................................................... 11 5. Electrical characteristics .............................................................................................................................................................. 16 5.1. Maximum ratings .................................................................................................................................................................... 16 5.2. Static electrical characteristics ............................................................................................................................................... 18 5.3. Dynamic electrical characteristics .......................................................................................................................................... 26 5.4. Timing diagrams .................................................................................................................................................................... 29 6. Functional description .................................................................................................................................................................. 32 6.1. Introduction ............................................................................................................................................................................ 32 6.2. Functional pin description ...................................................................................................................................................... 32 7. Functional device operation ......................................................................................................................................................... 36 7.1. Mode and state description .................................................................................................................................................... 36 7.2. LP modes ............................................................................................................................................................................... 37 7.3. State diagram ......................................................................................................................................................................... 39 7.4. Mode change ......................................................................................................................................................................... 40 7.5. Watchdog operation ............................................................................................................................................................... 40 7.6. Functional block operation versus mode ............................................................................................................................... 43 7.7. Illustration of device mode transitions .................................................................................................................................... 44 7.8. Cyclic sense operation during LP modes ............................................................................................................................... 45 7.9. Cyclic INT operation during LP VDD on mode ....................................................................................................................... 47 7.10. Behavior at power up and power down ................................................................................................................................ 48 7.11. Fail-safe operation ............................................................................................................................................................... 51 8. CAN interface .............................................................................................................................................................................. 55 8.1. CAN interface description ...................................................................................................................................................... 55 8.2. CAN bus fault diagnostic ........................................................................................................................................................ 58 9. LIN block ...................................................................................................................................................................................... 62 9.1. LIN interface description ........................................................................................................................................................ 62 9.2. LIN operational modes ........................................................................................................................................................... 63 10. Serial peripheral interface .......................................................................................................................................................... 64 10.1. High level overview .............................................................................................................................................................. 64 10.2. Detail operation .................................................................................................................................................................... 64 10.3. Detail of control bits and register mapping ........................................................................................................................... 68 10.4. Flags and device status ....................................................................................................................................................... 84 11. Typical applications ................................................................................................................................................................... 92 12. Packaging ................................................................................................................................................................................ 100 12.1. SOIC 32 package dimensions ........................................................................................................................................... 100 12.2. SOIC 54 package dimensions ........................................................................................................................................... 103 13. Revision history ....................................................................................................................................................................... 106 33903/4/5 2 NXP SemiconductorsSIMPLIFIED APPLICATION DIAGRAMS 1 Simplified application diagrams * = Optional 33905D V BAT (5.0 V/3.3 V) D1 Q2 Q1* VBAUX VCAUX VSUP1 VAUX VE VB V VDD DD VSUP2 RST SAFE DBG INT GND MOSI VSENSE SCLK SPI MCU MISO I/O-0 CS A/D MUX-OUT I/O-1 5V-CAN CANH TXD SPLIT RXD CAN Bus CANL TXD-L1 LIN-TERM 1 RXD-L1 LIN Bus LIN-1 TXD-L2 LIN- TERM 2 RXD-L2 LIN Bus LIN-2 Figure 1. 33905D simplified application diagram * = Optional 33905S V BAT (5.0 V/3.3 V) D1 Q2 Q1* VBAUX VCAUX VSUP1 VAUX VE VB V VDD DD VSUP2 SAFE RST DBG INT GND MOSI VSENSE SCLK SPI MCU MISO I/O-0 CS A/D MUX-OUT I/O-1 5V-CAN CANH TXD SPLIT RXD CAN Bus CANL TXD-L V BAT LIN-T RXD-L LIN Bus LIN I/O-3 Figure 2. 33905S simplified application diagram 33903/4/5 NXP Semiconductors 3

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